24
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
131,072 x 18, 262,144 x 18
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
Figure 19. Block Diagram of 131,072 x 36 and 262,144 x 36 Width Expansion
problems can be avoided by creating composite flags, that is, ANDing EF
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72V295/
72V2105 devices. D0-D17 from each device form a 36-bit wide input bus
and Q0-Q17 from each device form a 36-bit wide output bus. Any word width
can be attained by adding additional IDT72V295/72V2105 devices.
WRITE CLOCK (WCLK)
m + n
mn
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
nm + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR) #1
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
E
MPTY FLAG/OUTPUT READY (EF/OR)
#2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72V295
72V2105
EMPTY FLAG/OUTPUT READY (EF/OR)
#1
PARTIAL RESET (PRS)
IDT
72V295
72V2105
4668 drw 22
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
FIFO
#2
GATE
(1)
GATE
(1)
D0
-
Dm
DATA IN
Dm
+1 - Dn
Q
0
-
Qm
Qm
+1 - Qn
FIFO
#1
