25
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
131,072 x 18, 262,144 x 18
Figure 20. Block Diagram of 262,144 x 18 and 524,288 x 18 Depth Expansion
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72V295
72V2105
TRANSFER CLOCK
4668 drw 23
n
n n
FWFT/SI FWFT/SI
FWFT/SI
IDT
72V295
72V2105
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V295 can easily be adapted to applications requiring depths
greater than 131,072 and 262,144 for the IDT72V2105 with an 18-bit bus
width. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no
external logic necessary. The resulting configuration provides a total depth
equivalent to the sum of the depths associated with each single FIFO.
Figure 24 shows a depth expansion using two IDT72V295/72V2105 de-
vices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down") until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO's outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the
preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
