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FEBRUARY 2016
IDT72125
2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2665/1
©
CMOS PARALLEL-TO-SERIAL FIFO
1,024 x 16
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
25ns parallel port access time, 35ns cycle time
50MHz serial shift frequency
Wide x16 organization offering easy expansion
Low power consumption (50mA typical)
Least/Most Significant Bit first read selected by asserting the
FL/DIR pin
Four memory status flags: Empty, Full, Half-Full, and Almost-
Empty/Almost-Full
Dual-Port zero fall-through architecture
Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
Green parts available, see ordering information
DESCRIPTION:
The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial
FIFO. This FIFO features a 16-bit parallel input port and a serial output port with
1,024 word depths, respectively.
W
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RESET
LOGIC
FLAG
LOGIC
SERIAL OUTPUT
LOGIC
WRITE
POINTER
RAM
ARRAY
1,024 x 16
READ
POINTER
D
0
-
15
FF
RS
16
EXPANSION
LOGIC
RSIX
RSOX
FL/DIR
EF
HF
AEF
SOCP SO
The ability to buffer wide word widths (x16) make these FIFOs ideal for laser
printers, FAX machines, local area networks (LANs), video storage and disk/
tape controller applications.
Expansion in width and depth can be achieved using multiple chips. IDT’s
unique serial expansion logic makes this possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO) and one clock
pin (SOCP). The Least Significant or Most Significant Bit can be read first by
programming the DIR pin after a reset.
Monitoring the FIFO is eased by the availability of four status flags: Empty,
Full, Half-Full and Almost-Empty/Almost-Full. The Full and Empty flags prevent
any FIFO data overflow or underflow conditions. The Half-Full Flag is available
in both single and expansion mode configurations. The Almost-Empty/Almost-
Full Flag is available only in a single device mode.
The IDT72125 is fabricated using submicron CMOS technology.
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COMMERCIAL TEMPERATURE RANGE
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
PIN CONFIGURATION
PIN DESCRIPTIONS
PLASTIC THIN DIP (P28, order code: TP)
SOIC (SO28, order code: SO)
TOP VIEW
5
6
7
8
9
10
11
12
13
HF
D
2
D
3
D
4
GND
1
2
3
4
14
28
27
26
25
24
23
22
21
RSOX/AEF
FL/DIR
Vcc
SO
SOCP
20
19
18
17
16
15
D
1
D
0
W
D
13
D
14
D
15
D
12
FF
EF
RSIX
D
5
D
6
D
7
D
9
D
10
D
11
D
8
RS
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Symbol Name I/O Description
D0–D15 Inputs I Data inputs for 16-bit wide data.
RS Reset I When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array.
FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up.
W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset.
W Write I A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold
times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
SOCP Serial Output Clock I A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both
Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
FL/DIR First Load/Direction I This is a dual purpose input used in the width and depth expansion configurations. The First Load (FL)
function is programmed only during Reset (RS) and a LOW on FL indicates the first device to be loaded
with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift
direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first.
RSIX Read Serial In I In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX
Expansion is connected to RSOX (expansion out) of the previous device.
SO Serial Output O Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the
Direction pin programming. During Expansion the SO pins are tied together.
FF Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH,
the device is not full.
EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH,
the device is not empty.
HF Half-Full Flag O When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to half-full.
RSOX/AEF Read Serial O This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF output pin.
Out Expansion When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEF is HIGH, the device
Almost-Empty, is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a
Almost-Full Flag pulse is sent from RSOX to RSIX to coordinate the width, depth or daisy chain expansion.
VCC Power Supply Single power supply of 5V.
GND Ground Single ground of 0V.
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IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
STATUS FLAGS
Symbol Description Max Unit
VTERM Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TSTG Storage Temperature –55 to +125 °C
IOUT DC Output Current –50 to +50 mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input HIGH Voltage 2 V
VIL
(1)
Input LOW Voltage 0.8 V
TA Operating Temperature 0 +70 °C
RECOMMENDED DC OPERATING
CONDITIONS
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
IDT72125
Commercial
Symbol Parameter Min. Typ. Max. Unit
ILI
(1)
Input Leakage Current (Any Input) –1 1 μA
ILO
(2)
Output Leakage Current –10 10 μA
VOH Output Logic "1" Voltage IOUT = –2mA
(3)
2.4 V
VOL Output Logic "0" Voltage IOUT = 8mA
(4)
0.4 V
ICC1
(5)
Active Power Supply Current 50 100 mA
ICC2
(5,6,7)
Standby Current 4 8 mA
(W = RS = FL/DIR = VIH; SOCP = VIL)
ICC3
(5,6,7)
Power Down Current 1 6 mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0
ο
C to +70
ο
C)
Number of Words in FIFO
IDT72125 FF AEF HF EF
0HLHL
1–127 H L H H
128–512 H H H H
513–896 H H L H
897–1023 H L L H
1024 L L L H
NOTES:
1. Measurements with 0.4V VIN VCC.
2. SOCP = VIL, 0.4 VOUT VCC.
3. For SO, IOUT = -4mA.
4. For SO, IOUT = 16mA.
5. Tested with outputs open (IOUT = 0).
6. RS = FL/DIR = W = VCC - 0.2V; SOCP = 0.2V; all other inputs - VCC - 0.2.
7. Measurements are made after reset.

72125L25SOG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 1KX16 PARALLEL TO SERIAL
Lifecycle:
New from this manufacturer.
Delivery:
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