10
COMMERCIAL TEMPERATURE RANGE
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
NOTE:
1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half-Full Flag Output, FF = Full Flag Output.
TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE-
WIDTH/DEPTH COMPOUND EXPANSION MODE
Inputs Internal Status Outputs
Mode RS FL DIR Read Pointer Write Pointer EF HF, FF
Reset-First Device 0 0 X Location Zero Location Zero 0 1
Reset All Other Devices 0 1 X Location Zero Location Zero 0 1
Read/Write 1 X 0,1 X X X X
2665 drw16
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #6
SO
W
D
16-31
FL/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #4
SO
W
D
16-31
FL/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #2
SO
W
D
16-31
FL/DIR
EF
RSIX RSOX
HF
FF
SOCP
FIFO #5
SO
W
D
0-15
FL/DIR
EF
RSIX RSOX
HF
FF
SOCP
FIFO #3
SO
W
D
0-15
FL/DIR
EF
RSIX RSOX
HF
FF
SOCP
FIFO #1
SO
W
D
0-15
FL/DIR
ADDRESS
DECODER
74FCT138
00 01 10
SERIAL OUTPUT CLOCK
LOW ON RESET
HIGH ON RESET
FULL
FLAG
HALF-FULL
FLAG
EMPTY
FLAG
SERIAL DATA
OUT
PARALLEL DATA
IN
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
