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72125L25SOG

P1-P3P4-P6P7-P9P10-P11
7
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
Figure 6. Empty Boundary Condition Timing
Figure 7. Full Boundary Condition Timing
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
NOTES:
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
NOTE:
1. Single Device Mode will not tri-state but will retain the last valid data.
2665 drw09
SOCP
W
EF
t
REFSO
t
WEF
0 1 n-1
SO
DATA
IN
t
SOCEF
t
SOLZ
t
SOPD
NOTE 1
NOTE 2
2665 drw10
SOCP
W
FF
t
WPF
0
SO
DATA
IN
DATA
IN
VALID
1 n-1
t
SOCFF
t
WFF
t
DS
t
DH
t
SOPD
NOTE 1
NOTE 1
DATA
OUT
VALID
2665 drw11
SOCP
W
HF
t
WF
AEF
AEF
HALF-FULL (1/2) HALF-FULL
7/8 FULL 7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST-EMPTY
(1/8 FULL-1)
t
WF
ALMOST-FULL (7/8 FULL + 1)
1/8 FULL
HALF-FULL + 1
t
SOCF
t
SOCF
8
COMMERCIAL TEMPERATURE RANGE
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
2665 drw13
SO
SOCP
RSOX/AEF
D
0-15
ALMOST-EMPTY/FULL FLAG
SERIAL DATA
OUT
PARALLEL DATA
IN
RSIX
SERIAL OUTPUT CLOCK
V
CC
OPERATING CONFIGURATIONS
SINGLE DEVICE MODE
The device must be reset before beginning operation so that all flags are
set to location zero. In the standalone case, the RSIX line is tied HIGH and
indicates single device operation to the device. The RSOX/AEF pin defaults to
AEF and outputs the Almost-Empty and Almost-Full Flag.
WIDTH EXPANSION MODE
In the cascaded case, word widths of more than 16 bits can be achieved
by using more than one device. By tying the RSOX and RSIX pins together,
as shown in Figure 11, and programming which is the Least Significant Device,
a cascaded serial word is achieved. The Least Significant Device is pro-
grammed by a LOW on the FL/DIR pin during reset. All other devices should
be programmed HIGH on the FL/DIR pin at
reset.
NOTE:
1. Pointer will increment if appropriate flag is HIGH
Figure 10. Single Device Configuration
2665 drw12
FL/DIR
RS
SOCP
RSIX
RSOX
t
FLH
t
DIRS
15 0
t
FLS
t
DIRH
t
SOXD1
t
SOXD2
t
SIXS
t
RSIXPW
Figure 9. Serial Read Expansion
TABLE 1 — RESET AND FIRST LOAD TRUTH TABLE-
SINGLE DEVICE CONFIGURATION
Inputs Internal Status Outputs
Mode RS FL DIR Read Pointer Write Pointer AEF, EF FF HF
Reset 0 X X Location Zero Location Zero 0 1 1
Read/Write 1 X 0,1 Increment
(1)
Increment
(1)
XX X
The Serial Data Output (SO) of each device in the serial word must be tied
together. Since the SO pin is three stated, only the device which is currently
shifting out is enabled and driving the 1-bit bus. NOTE: After reset, the level on
the FL/DIR pin decides if the Least Significant or Most Significant Bit is read first
out of each device.
The three flag outputs, Empty (EF), Half-Full (HF) and Full (FF), should
be taken from the Most Significant Device (in the example, FIFO #2). The
Almost-Empty/Almost-Full flag is not available. The RSOX pin is used for
expansion.
9
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
COMMERCIAL TEMPERATURE RANGE
2665 drw15
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #3
SO
W
D
0-15
FL/DIR
ADDRESS
DECODER
74FCT138
00
01
10
FULL
FLAG
HALF-FULL
FLAG
EMPTY
FLAG
HIGH AT RESET
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #2
SO
W
D
0-15
FL/DIR
HIGH AT RESET
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #1
SO
W
D
0-15
FL/DIR
LOW AT RESET
SERIAL OUTPUT CLOCK
SERIAL DATA
OUT
PARALLEL DATA
IN
OPERATING CONFIGURATIONS
SINGLE DEVICE MODE
The IDT72125 can easily be adapted to applications requiring greater than
1,024 words. Figure 12 demonstrates Depth Expansion using three IDT72125s
and an 74FCT138 Address Decoder. Any depth can be attained by adding
additional devices. The Address Decoder is necessary to determine which
FIFO is being written. A word of data must be written sequentially into each FIFO
so that the data will be read in the correct sequence. These devices operate
in the Depth Expansion Mode when the following conditions are met:
1. The first device must be programmed by holding FL LOW at Reset. All other
devices must be programmed by holding FL HIGH at reset.
2. The Read Serial Out Expansion pin (RSOX) of each device must be tied
to the Read Serial In Expansion pin (RSIX) of the next device (see Figure
12).
3. External logic is needed to generate composite Empty, Half-Full and Full
Flags. This requires the ORing of all EF, HF and FF Flags.
4. The Almost-Empty and Almost-Full Flag is not available due to using the
RSOX pin for expansion.
COMPOUND EXPANSION (DAISY CHAIN) MODE
These FIFOs can be expanded in both depth and width as Figure 13 indicates:
1. The RSOX-to-RSIX expansion signals are wrapped around sequentially.
2. The write (W) signal is expanded in width.
3. Flag signals are only taken from the Most Significant Devices.
4. The Least Significant Device in the array must be programmed with a LOW
on FL/DIR during reset.
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
2665 drw14
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #2
SO
W
D
16-31
FL/DIR
FULL FLAG
HALF-FULL FLAG
EMPTY FLAG
HIGH AT RESET
SERIAL OUTPUT CLOCK
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #1
SO
W
D
0-15
FL/DIR
LOW AT RESET
SERIAL DATA
OUT
PARALLEL DATA
IN
Figure 11. Width Expansion for 32-bit Parallel Data In
P1-P3P4-P6P7-P9P10-P11

72125L25SOG

Mfr. #:
Buy 72125L25SOG
Manufacturer:
IDT
Description:
FIFO 1KX16 PARALLEL TO SERIAL
Lifecycle:
New from this manufacturer.
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