
SE4110L
GPS Receiver IC
DST-00002 ! Rev 6.4 ! May-26-2009 12 of 22
Logic Level Characteristics
Conditions: VCC = VDD = 3.3 V, TA = 25 $C
Symbol Parameter Note Min. Typ. Max. Unit
VIH Logic High Input Voltage 1 0.7VDDN - VDDN V
VIL Logic Low Input Voltage 1 0 - 0.3VDDN V
IIH Input Current Logic High Voltage 1 - 200 - nA
I
IH_RX_EN
Input Current Logic High Voltage for
RX_EN Input (pin 23)
2 - 2.2 - "A
IIL Input Current Logic Low Voltage 1 - -200 - nA
C
ILOAD
Input Load Capacitance 1 - - 2 pF
V
OH
Logic High Output Voltage 3 V
DDN
- 0.1V - VDDN V
V
OL
Logic Low Output Voltage 3 0 - 0.1 V
IOH Output Current Logic High Voltage 3, 4 - 1.45 - mA
IOL Output Current Logic Low Voltage 3, 4 - -1.45 - mA
C
OLOAD
Output Load Capacitance 3 - - 10 pF
Note: (1) Applies to all Logic pins used as inputs: AGC_DIS (pin 6), FREF0 (pin 12), FREF1 (pin 13),
FREF2 (pin 14), OSC_EN (pin 19) and RX_EN (pin 23).
(2) Applies to RX_EN (pin 23) only. Figure dominated by 1.5 M! (nom) on-chip pull-down resistor.
(3) Applies to all Logic pins used as outputs: CLK_OUT (pin 9), SIGN (pin 10), and MAG (pin 11).
(4) Output Current set at Nominal level; no Current Setting Resistor on RVI (pin 20). Positive value
indicates current source; negative value indicates current sink.
Logic Output Current Drive Adjustment Settings
The Logic Outputs on the SE4110L can be adjusted to compensate for parasitics in application board layout. This can
be achieved by adding a resistor between RVI (pin 20) and VDDQ (pin 17) as shown below.
The additional interface capacitance of PCB tracking and connectors between the SE4110L output and baseband IC
input is included in these figures.
These figures are Typical only, and are not guaranteed across temperature and silicon process.
Conditions: VCC = VDD = 3.3 V, TA = 25 $C
Current Setting Resistor Value
(RVI (pin 20) to VDDQ (pin 17))
(!)
Maximum Allowable
Capacitive Loading
(pF)
Current Drive
Level
Not Fitted
5 Nominal
100K 6 X 1.2
39K 7 X 1.4
0R 10 X 2.0