SE4110L
GPS Receiver IC
DST-00002 ! Rev 6.4 ! May-26-2009 4 of 22
Pin No. Name Description Connection
19 OSC_EN Crystal oscillator enable
If using TCXO reference source
(NO crystal oscillator needed):
Connect to VSSN / GND
If using Crystal reference source, with
crystal oscillator:
Connect to VDD
20 RVI Program baseband output drive current
Leave unconnected
or
Connect via a resistor to analogue VCC
for up to 2x output drive current
21 MIX_IN Mixer input DC coupled RF input to RF Mixer
22 VCC
Analogue Power supply for RF front
end
Connect to VCC
23 RX_EN Receiver enable
Connect to VDD to enable Radio
Connect to VSSN / GND to disable
Radio
24 LNA_OUT LNA RF output
RF output from LNA. DC blocked, with
10 k! (nom) DC impedance to ground.
Die Pad GND Ground connection Main IC GND Connection
SE4110L
GPS Receiver IC
DST-00002 ! Rev 6.4 ! May-26-2009 5 of 22
Functional Description
LNA
The internal LNA allows a high-performance, low-
power GPS receiver to be completed without using
any additional active components.
The GPS L1 input signal which is applied to LNA_IN
(pin 3), is a spread-spectrum signal centered on
1575.42 MHz with a 1.023 Mbps BPSK modulation.
The signal level at the antenna is typically -130 dBm
in open-sky conditions, dropping to below -150 dBm
in masked signal areas (e.g. indoors). The LNA noise
figure is the largest contributor to the sensitivity so it is
an important parameter; the lower, the better.
The LNA input requires a minimum of external
matching components to achieve good RF gain with
minimal noise figure: only a single series inductor and
single shunt capacitor are required. The input requires
a DC blocking capacitor if circuitry prior to the LNA
has a DC bias. Although attention should be paid to
track lengths and interference throughout the design,
the LNA input matching circuit is the only RF circuit
critically sensitive to layout.
The LNA output includes internal 50 "#matching for
connection to the mixer input, either directly or via an
optional external filter.
In applications where the internal LNA is not required,
the LNA can be disabled by connecting VCC_LNA
(pin 1) to GND. This will save approximately 1.9 mA
of active current.
Mixer RF Input
The mixer RF input, MIX_IN (pin 21), is a single-
ended 50 ! input designed to interface either to
LNA_OUT (pin 24) or to the output of an external
filter. An external active antenna can also be
connected to the mixer input.
The image reject mixer ensures that the receiver’s full
sensitivity is achieved without an external filter. For
applications where additional selectivity is required,
an external filter can be added between the
LNA_OUT and MIX_IN pins.
IF Filter
The SE4110L includes a fully integrated Intermediate
Frequency (IF) filter which provides excellent
interference rejection with no additional external
components. The filter has a 3rd order Butterworth
bandpass response.
The bandpass response has a nominal bandwidth of
2.2 MHz; the nominal center frequency is preset to
4.092 MHz. These parameters ensure very low
implementation loss in all frequency plan
configurations.
AGC and ADC
The SE4110L features a linear IF chain with 2-bit
SIGN / MAG ADC. SIGN is on pin 10, and MAG on
pin 11.
An Automatic Gain Control (AGC) system is included.
This provides over 40 dB of gain control range so that
the output signal level is held at an optimum level at
the input of the ADC.
The MAG data controls the AGC loop, such that the
MAG bit is active (HIGH) for approximately 33 % of
the time.
The SIGN and MAG signals are latched by the rising
edge of the sample clock, CLK_OUT (pin 9). The
SIGN and MAG signals are best sampled by the GPS
baseband IC on the rising edge of CLK_OUT, for
optimum sample and hold in the ADC.
The AGC time constant is determined by a single
external capacitor, connected between VAGC (pin 5),
and VSSN / GND. The settling-time of the AGC is
within 10ms with a 10nF capacitor.
The AGC system also features a control-inhibit
facility, via AGC_DIS (pin 6). By connecting AGC_DIS
to VDDN, the internal AGC controller is inhibited, and
the gain held at the level set prior to the inhibition.
While the AGC controller is inhibited, it is possible to
control the AGC gain from an external source by
applying a low-impedance voltage to VAGC (pin 5).
PLL and Loop Filter
The entire phase-locked loop (PLL) generating the
local oscillator for the mixer is contained on-chip, with
the exception of the PLL loop filter.
A PLL loop filter can be implemented by attaching a
series capacitor (220 pF) and a resistor (33 k!)
between VTUNE (pin 18) and GND / VSSN. The PLL
follows a classic 3
rd
-order response; this is achieved
in conjunction with an on-chip 10 pF capacitor
connected between VTUNE and GND / VSSN.
Typical PLL Loop Bandwidth is set to be 200 kHz.
The reference frequency for the PLL may be supplied
either externally or using the on-chip crystal oscillator.
SE4110L
GPS Receiver IC
DST-00002 ! Rev 6.4 ! May-26-2009 6 of 22
Crystal Oscillator
The SE4110L features a very low power crystal
oscillator which may be used to provide the frequency
reference. The oscillator is designed to work with
parallel resonant crystals or be driven from an
external TCXO.
The crystal drive level is carefully controlled so that
the device is well-suited for use with miniature surface
mount crystals. The crystal oscillator is a Pierce
configuration, as shown in the diagram below. The
application circuit is designed to work with parallel
resonant crystals with a parallel load capacitance of
approx. 10 pF.
SE4110L Crystal Oscillator
(15)
(16)
XTAL
XTAL 1
XTAL 2
SE4110
22pF 22pF
The PCB layout should avoid excessive track length
between XTAL1 (pin 15) and XTAL2 (pin 16) and the
crystal. The capacitors at each terminal of the crystal
should be mounted adjacent to the crystal and have a
low impedance connection to the ground plane in
order to maintain the Oscillator Loop Gain and Phase-
Noise performance under all conditions.
The SE4110L can also be used with an external
TCXO as shown below. The TCXO should provide a
clipped sinewave signal. The XTAL2 pin should be left
unconnected in this configuration.
SE4110L TCXO Connection
(15)
(16)
XTAL 1
XTAL 2
SE4110
TCXO
10nF
Clock and Data Output Coupling
The high input sensitivity achieved by the SE4110’s
internal LNA requires careful control of harmonically
related sources of interference.
For this reason the CLK_OUT (pin 9), SIGN (pin 10)
and MAG (pin 11) outputs provide carefully controlled
current and slew-rate. The data and clock outputs of
the SE4110L are specified to drive up to 10pF load
(max standard CMOS input capacitance). The output
drive of the SE4110L can be adjusted with a resistor
connected between VDDQ (pin 17) and RVI (pin 20),
as shown in the Logic Level Characteristics section
below.
The output current drive is determined by a bias
current ratio internal to the SE4110L and the external
resistor.
Frequency Plan Selection
The SE4110L supports operation with a range of
reference frequencies, aimed at both ‘traditional’ GPS
and the emerging cellular GPS applications.
The supported frequency plans are tabulated below.
A (+) sign on the IF (output) frequency denotes that
the digital signal is not spectrally inverted with respect
to the RF input at 1575.42 MHz, as a result of the RF
mixer using a low-side Local Oscillator.
A (-) sign indicates that there is a spectral inversion to
be taken into account, as a result of the RF mixer
using a high-side Local Oscillator.
Supported Frequency Plans
Reference
frequency
Intermediate
Frequency
(SIGN/MAG
pins)
Sample clock
(CLK_OUT
pin)
13 MHz -4.080 MHz 19.5 MHz
16.368 MHz +4.092 MHz 16.368 MHz
19.5 MHz -4.080 MHz 19.5 MHz
26 MHz -4.080 MHz 19.5 MHz
The frequency plan may be configured by connecting
the FREF<2:0> inputs (pins 12, 13, and 14) to RX_EN
(pin 23) for Logic ‘1’, or VSSN for Logic ‘0’.

SE4110L-R

Mfr. #:
Manufacturer:
Skyworks Solutions, Inc.
Description:
RF Receiver L-1 Band GPS NF 1.6dB
Lifecycle:
New from this manufacturer.
Delivery:
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