SE4110L
GPS Receiver IC
DST-00002 ! Rev 6.4 ! May-26-2009 13 of 22
Logic Timing Characteristics
Conditions: C
L
# 10 pF, V
CC
= V
DD
= 3.3 V, T
A
= 25 $C at Maximum Buffer Current
Symbol Parameter Note Min. Typ. Max. Unit
t
PER
Clock Period - 51.2 - 61.1 ns
t
PWL
Clock Low Width 1 10 - - ns
t
PWH
Clock High Width 1 10 - - ns
t
SETUP
Setup Time 1 10 - - ns
t
HOLD
Hold Time - 1.7 - - ns
t
RCLK
Rise Time CLK_OUT, 10 - 90% 1 - - 17 ns
t
R/F
Rise and Fall Time SIGN/MAG, 10 - 90% 1 - - 17 ns
Note: (1) Values dependent on output drive level, determined by resistor on RVI (pin 20).
Logic Output Data Timing Diagram
t
SETUP
t
HOLD
t
R/F(10-90%)
t
PER
t
PWH
t
PWL
CLK_OUT
SIGN, MAG
t
RCLK(10-90%
Conditions: (1) Cload SIGN/MAG # 10pF
(2) Cload CLK_OUT # Cload SIGN/MAG
(3) Output drive set to Maximum: RVI (pin 20) directly connected to VDDQ (pin 17)
