SE4110L
GPS Receiver IC
DST-00002 ! Rev 6.4 ! May-26-2009 7 of 22
The following truth table gives the settings for
hardware configuration.
FREF Hardware Configuration
Reference
frequency
Selection
value
(FREF<2:0>)
16.368 MHz 000
13 MHz 100
19.5 MHz 101
26 MHz 110
Power Management
The SE4110L has 3 levels of power control: standby,
oscillator only and active. These are controlled by two
enable pins, RX_EN (pin 23) and OSC_EN (pin 19). A
table showing the Power Control states follows:
SE4110L Power Control States
RX_EN OSC_EN Power state
0 0 Standby
0 1 Oscillator only
1 0
Fully active
(external reference)
1 1
Fully active
(internal oscillator)
In standby mode, all circuits are off and the device
consumes only leakage current.
The oscillator-only mode is provided for applications
where it is required to keep the sample clock
(CLK_OUT (pin 9)) available when active GPS
reception is not needed. This feature allows a clock to
be maintained with reduced current consumption, but
is not available in the 13 MHz mode.
There are two settings in the SE4110L Power Control
States table for fully active operation depending on
whether an external signal or the internal crystal
oscillator is used to provide the reference frequency.
When using an external reference, approximately
0.4 mA of supply current is saved.
The RX_EN input, (pin 23), has a 1.5M! pull-down
resistor to GND, on-chip. This ensures that the RFIC
will put itself in standby (or oscillator only mode if
OSC_EN is controlled separately) when the RX_EN
controller on the baseband is tri-stated to an
impedance much greater than 1.5M!.
The internal LNA can be disabled by connecting the
Vcc supply connection to the LNA, VCC_LNA (pin 1)
to GND. This may be desirable in some applications,
and prevents the LNA from consuming any current,
saving approximately 1.9 mA.
Logic Interfacing
The SE4110L Logic Inputs can either be driven from
an external baseband IC, or permanently set by
connecting to either VDDN (pin 8) for Logic ‘1’, or
VSSN (pin 7) for Logic ‘0’. The digital interface on the
SE4110L, supplied from VDDN, has been designed to
operate at the same voltage as the GPS baseband IC
across a wider voltage range than the RF sections of
the device. It will accommodate the lower voltage
baseband ICs down to 1.7 V. The SE4110L Logic
Input signals are shown in the following table:
SE4110L Logic Inputs
Pin Name Description Logic
6 AGC_DIS AGC Inhibit
Input
‘1’ Hold AGC Gain
‘0’ Enable AGC
12 FREF0 Frequency
Reference
Select (bit 0)
13 FREF1 Frequency
Reference
Select (bit 1)
14 FREF2 Frequency
Reference
Select (bit 2)
See table:
“FREF Hardware
Configuration”
19 OSC_EN Crystal
oscillator
enable
‘1’ Crystal source
with osc enabled
‘0’ TCXO source
with osc disabled
23 RX_EN Radio enable ‘1’ Enable radio
‘0’ Standby mode
Power-up Sequencing
To use the SE4110L device with either the FREF0
(pin 12), FREF1 (pin 13) or FREF2 (pin 14)
connections set to a logic ‘1’ to enable one of the
Hardware Configurations described above, it is
recommended that the pins concerned are connected
directly to the signal driving RX_EN (pin 23). The
RX_EN signal should be set to VDD levels (logic ‘1’) a
short time (>100us) after main VCC/VDD power is
applied to the SE4110L device.
