AK4112BVM Datasheet AK4112BVM | P13-P15

[AK4112B]

MS0078-E-03 2012/01

- 13 -

 System Reset and Power-Down

The AK4112B has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The

RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled.

The AK4112B should be reset once by bringing PDN pin = “L” upon power-up.

PDN Pin (Pin #7):

All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= “L”. All the

registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled.

RSTN Bit (Address 00H; D0):

All the registers except PWN and RSTN are initialized by bringing RSTN bit = “0”. The internal timings are

also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is

disabled.

PWN Bit (Address 00H; D1):

The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks are stopped. The registers

are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.

 Biphase Input and Through Output

Four receiver inputs (RX1-4) are available in Serial Control Mode. Each input includes amplifier corresponding to

unbalance mode and can accept the signal of 350mV or more. IPS0-1 selects the receiver channel, and OPS0-1 selects the

source of the bit stream driving the transmit channel (TX). The TX output can be stopped by setting TXE bit “0”.

IPS1 IPS0 INPUT Data

0 0 RX1 Default

0 1 RX2

1 0 RX3

1 1 RX4

Table 9. Recovery data select

OPS1 OPS0 INPUT Data

0 0 RX1 Default

0 1 RX2

1 0 RX3

1 1 RX4

Table 10. Output data select

[AK4112B]

MS0078-E-03 2012/01

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AK4112B

0.1uF

75:

Coax

0.47nF

Note

Figure 1. Consumer Input Circuit (Coaxial Input)

Note: In case of coaxial input, if a coupling level to this input from the next RX input line

pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is

possible to lower the coupling level by adding this decoupling capacitor.

AK4112B

470

O/E

Optical Receiver

Optical

Fiber

Figure 2. Consumer Input Circuit (Optical Input)

In case of coaxial input, as the input level of RX line is small, in Serial Mode, be careful not to crosstalk among RX input

lines. For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is

available and RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”.

The AK4112B includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor

network. The T1 in Figure 3 is a transformer of 1:1.

DVSS

cable

Vdd R1 R2

3.3V 240

150

3.0V 220

150

Figure 3. TX External Resistor Network

[AK4112B]

MS0078-E-03 2012/01

- 15 -

 Error Handling

There are the following five factors which ERF pin goes “H”. ERF pin shows the status of the internal PLL operation and

it is “L” when the PLL is OFF (Clock Operation Mode 1).

1. Unlock Error : “H” when the PLL goes UNLOCK state.

2. Parity Error : Updated every sub-frame cycle.

3. Biphase Error : Updated every sub-frame cycle

4. Frame length Error : Updated every sub-frame cycle

5. STC (Status Change) flag=“1” : Holds “1” until reading 03H.

In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes ”H”, it

maintains “H” for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins

when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect.

When unlock state, the channel status bits are not updated and the previous data is maintained.

Error AUTO SDTO V

Unlock Error “L” “L” “L”

Parity Error Output Previous Data Output

Biphase Error Output Previous Data Output

Frame Length Error Output Previous Data Output

Table 11. Error handling (Parallel Mode)

In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and

Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked

by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the

last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made

every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after

reset.

Once ERF pin goes ”H”, it maintains “H” for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors

(In case of STC, from STC flag “1” to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes “1”,

it returns “0” by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the

previous data is maintained.

Error

& Status

UNLOCK PAR BIP FRERR STC AUTO SDTO V TX

Unlock Error 1 0 0 0 0 “L” “L” “L” Output

Parity Error 0 1 0 0 0 Output Previous Data Output Output

Biphase Error 0 0 1 0 0 Output Previous Data Output Output

Frame Length Error 0 0 0 1 0 Output Previous Data Output Output

Status change 0 0 0 0 1 Output Output Output Output

Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

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