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AK4112BVM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
[AK4112B]
MS0078-E-03 2012/01
- 22 -
Register Definitions
Reset & Initialize
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Clock & Power down Control 0 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN
R/W RD R/W R/W R/W R/W R/W R/W R/W
default 0 0 0 0 0 0 1 1
RSTN: Timing Reset & Register Initialize
0: Reset & Initialize
1: Normal Operation
PWN: Power Down
0: Power down
1: Normal Operation
OCKS1-0: Master Clock frequency Select
CM1-0: Master Clock Operation Mode Select
BCU: Block start & C/U output Mode
When BCU=1, the 3 output pins change another function.
MCKO2 pino B; block start signal
AUTO pino C bit
FS96 pino U bit
The block signal goes high at the start of frame 0 and remains high until the end of frame 31.
(B, C, U, V output timing at RX mode, Master mode)
B
C (or U,V)
LRCK
C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)C(R191)
1/4fs
SDTO
(except I
2
S)
L191 R191 L0 R30
R31
L31
SDTO
(I
2
S)
L191 R191 L30
L31
R30
L0
R190
R0
[AK4112B]
MS0078-E-03 2012/01
- 23 -
Input/Output Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Input/Output Control MPAR MSTC CS12 TXE IPS1 IPS0 OPS1 OPS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
default 1 0 0 1 0 0 0 0
OPS1-0: Output Through Data Select
IPS1-0: Input Recovery Data Select
TXE: TX Output Enable
0: Disable. TX output pin is placed in a high impedance state.
1: Enable
CS12: Channel Status Select
0: Channel 1
1: Channel 2
Selects which channel status is used to derive AUDION, PEM, FS1 and FS0.
The de-emphasis filter, however, is always controlled by channel 1 in the Parallel Mode.
MSTC: Status change flag mask bit
This bit is low to mask status change from being reported by ERF.
MPAR: Parity mask bit
This bit is low to mask Parity Error, Biphase Error and Frame Length Error from being reported by
ERF.
Format & De-emphasis Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Format & De-emphasis Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
default 0 1 0 0 1 0 1 0
V/TX: V/TX Output Select
0: Validity Flag Output. This output is updated every fs cycle.
1: TX
DFS: 96kHz De-emphasis Control
DEM1-0: 32, 44.1, 48kHz De-emphasis Control
DEAU: De-emphasis Auto Detect Enable
0: Disable
1: Enable
DIF2-0: Audio Data Format Control
[AK4112B]
MS0078-E-03 2012/01
- 24 -
Receiver Status 1
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Receiver status 1 ERF 0 AUDION AUTO PEM FS1 FS0 RFS96
R/W RD RD RD RD RD RD RD RD
default 0 0 0 0 0 0 0 0
RFS96: 96kHz Sampling Detect at Recovery Mode.
0: fs=54kHz or less.
1: fs=88.2kHz or more
FS1-0: Sampling Frequency Output
PEM: Pre-emphasis Output
0: OFF
1: ON
This bit is made by encoding channel status bits.
AUTO: Non-PCM Auto Detect
0: No detect
1: Detect
This function is the same as AUTO pin.
AUDION: Audio bit Output
0: Audio
1: Non Audio
ERF: Unlock or Parity Error or Status change
0: No Error or No change
1: Error or Change
This function is the same as ERF pin. This bit goes “1” when Unlock Error, Parity Error, Biphase
Error, Frame Length Error or Status Change occurs. If MPAR=0 & MSTC=0, only an unlock error
is reported.
Receiver Status 2
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H Receiver status 2 CV STC CRC UNLOCK V FRERR BIP PAR
R/W RD RD RD RD RD RD RD RD
default 0 0 0 0 0 0 0 0
PAR: Parity Status (0:No Error, 1:Error)
It is high if Parity Error is detected in the sub-frame. PAR is unaffected by the state of MPAR.
BIP: Biphase Status (0:No Error, 1:Error)
FRERR: Frame Error Status (0:No Error, 1:Error)
V: Validity bit (0:No Error, 1:Error)
UNLOCK: PLL Lock status (0:Lock, 1:Unlock)
CRC: Cyclic Redundancy Check (0:No Error, 1:Error on either channel)
STC: Status change flag of Receiver status 1 (0:No change, 1:change)
This flag goes “H” when the latest value of D5-0 in Receiver Status 1(03H) is different from the
previous value. This comparison is made at every fs cycle. This bit returns to “L” by reading
Receiver Status 1(03H). The flag is disabled during the first block after Reset.
CV: Channel Status Validity (0:Valid, 1:Not Valid, data is updating)
This signal goes “H” at the start of frame 0 and maintains “H” until the end of frame 31.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

AK4112BVM

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IC RCVR DGTL AUD QUAD 28SSOP
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