[AK4112B]
MS0078-E-03 2012/01
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Command
ERF
MCKO, BICK,
LRCK
SDTO
STC bit
V
READ 03H
Reset
(ch. status ) (state B)(state A )
(status change )
ERF Hold Time
Hold “1”
ERF pin timing at Status Change
error(UNLOCK,
PAR, BIP, FRERR)
ERF
SDTO(UNLOCK)
Vpin (UNLOCK)
MCKO,BICK,LRCK
(UNLOCK)
Vpin
(except UNLOCK)
Previous Data
register (UNOCK,
PAR, BIP, FRERR)
Hold ”1”
Command READ 04H
MCKO,BICK,LRCK
(except UNLOCK)
(fs: around 20kHz)
SDTO
(except UNLOCK)
ERF Hold Time
Reset
(error)
Free Run
ERF pin timing at UNLOCK, PAR, BIP, FRERR error
[AK4112B]
MS0078-E-03 2012/01
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PD pin ="L" to "H"
Read 03H
STC is reset, ERF pin ="L"
Read 04H
Mute = "H"
ERF pin ="H"
Read 03H
STC is reset, ERF pin ="L"
Read 04H
ERF pin ="H"
Mute="L"
NO
YES
YES
Initialize
Figure 4. Error handling sequence Example
[AK4112B]
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Audio Serial Interface Format
The DIF0, DIF1 and DIF2 pins as shown in Table 13 can select eight serial data formats. In all formats the serial data is
MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on
the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to
128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the
last 4LSBs are auxiliary data (see Figure 5).
When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4112B continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4112B
output “0” from SDTO. In case of using DAUX pin, the data is transformed and output from SDTO. DAUX pin is used
in Clock Operation Mode 1, 3 and unlock state of Mode 2.
The input data format to DAUX should be left justified except in Mode5 and 7(Table 13). In Mode5 or 7, both the input
data format of DAUX and output data format of SDTO are I
2
S. Mode6 and 7 are Slave Mode that is corresponding to the
Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2.
The initial state of the audio format is the Master Mode upon the power-up. Therefore, if the audio format is changed to
the Slave Mode after power-up, the setting of the external clocks should be careful until completing to set the control
registers.
0 34 781112 27 28 29 30 31
preamble Aux.
LSB MSB
VUCP
sub-frame of IEC958
023
AK4112B Audio Data (MSB First)
LSBMSB
Figure 5. Bit configuration
LRCK BICK
Mode DIF2 DIF1 DIF0 DAUX SDTO
I/O I/O
0 0 0 0 24bit, Left justified 16bit, Right justified H/L O 64fs O
1 0 0 1 24bit, Left justified 18bit, Right justified H/L O 64fs O
2 0 1 0 24bit, Left justified 20bit, Right justified H/L O 64fs O
3 0 1 1 24bit, Left justified 24bit, Right justified H/L O 64fs O
4 1 0 0 24bit, Left justified 24bit, Left justified H/L O 64fs O Default
5 1 0 1 24bit, I
2
S 24bit, I
2
S L/H O 64fs O
6 1 1 0 24bit, Left justified 24bit, Left justified H/L I 64-128fs I
7 1 1 1 24bit, I
2
S 24bit, I
2
S L/H I 64-128fs I
Table 13. Audio data format

AK4112BVM

Mfr. #:
Manufacturer:
Description:
IC RCVR DGTL AUD QUAD 28SSOP
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New from this manufacturer.
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