[AK4112B]
MS0078-E-03 2012/01
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Timing Diagram
tLRB
LRCK
BICK
SDTO
tBSD
tBLR tBCKL tBCKH
tLRM
50%DVDD
50%DVDD
50%DVDD
DAUX
50%DVDD
tDXS tDXH
Serial Interface Timing (Slave Mode)
LRCK
BICK
SDATA
tBSD
tMBLR
50%DVDD
50%DVDD
50%DVDD
DAUX
tDXH
50%DVDD
tDXS
Serial Interface Timing (Master Mode)
tCCKL
CSN
CCLK
tCDS
CDTI
tCDH
tCSS
C0 A4
tCCKH
CDTO
Hi-Z
R/W
C0
50%DVDD
50%DVDD
50%DVDD
WRITE/READ Command Input Timing
[AK4112B]
MS0078-E-03 2012/01
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tCSW
CSN
CCLK
CDTI D2 D0
tCSH
CDTO
Hi-Z
D1D3
50%DVDD
50%DVDD
50%DVDD
WRITE Data Input Timing
CSN
CCLK
tDCD
CDTO
D7 D6
CDTI
A1 A0
D5
Hi-Z
50%DVDD
50%DVDD
50%DVDD
50%DVDD
READ Data Output Timing 1
CSN
CCLK
tCCZ
CDTO
D2 D1
CDTI
D0
D3
tCSW
tCSH
50%DVDD
50%DVDD
50%DVDD
50%DVDD
READ Data Input Timing 2
tPW
PDN
30%DVDD
Power Down & Reset Timing
[AK4112B]
MS0078-E-03 2012/01
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OPERATION OVERVIEW
Non-PCM (AC-3, MPEG, etc.) Stream Detect
The AK4112B has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC958 Interface” is detected, the AUTO goes “H”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “H”. Once the AUTO is set
“H”, it will remain “H” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers
0DH-10H.
Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz
detect output pin FS96 goes “H” when the sampling rate is 88.2kHz or more and “L” at 54kHz or less. In X’tal Mode, the
FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.
Master Clock
The AK4112B has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2.
No. OCKS1 OCKS0 MCKO1 MCKO2 X’tal fs (kHz)
0 0 0 256fs 256fs 256fs 32, 44.1, 48, 96 Default
1 0 1 256fs 128fs 256fs 32, 44.1, 48, 96
2 1 0 512fs 256fs 512fs 32, 44.1, 48
3 1 1 Test Mode
Table 1. Master clock frequencies select
Clock Operation Mode
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the
control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the
clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.
Mode CM1 CM0
UNLOCK
PLL X'tal Clock source
FS96
SDTO
0 0 0 - ON OFF PLL RFS96 RX
Default
1 0 1
-
OFF ON X'tal
XFS96
DAUX
0 ON ON PLL RFS96 RX
2 1 0
1
ON ON X'tal
XFS96
DAUX
3 1 1 - ON ON X'tal XFS96 DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Table 2. Clock Operation Mode select

AK4112BVM

Mfr. #:
Manufacturer:
Description:
IC RCVR DGTL AUD QUAD 28SSOP
Lifecycle:
New from this manufacturer.
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