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NCN6000DTB

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NCN6000
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13
Card VCC, Card CLOCK and Card Detection
Polarity Programming
The CRD_VCC and CLOCK_IN programming options
allows matching the system frequency with the card clock
frequency, and to select 3.0 V or 5.0 V CRD_VCC supply.
The CRD_DET programming option allows the usage of
either Normally Open or Normally Close detection switch.
Table 3 highlights the A0, A1, PGM and I/O logic states for
the possible options. The default power up reset condition
is state 1: asynchronous clock, ratio 1/1, CRD_CLK
active, CRD_DET = Normally Open, CRD_VCC = 3.0 V.
All states are latched for each output variable in
programming mode at the positive going slope of Chip
Select [CS] signal. It is the system designer’s responsibility
to set up the options needed to match the chip with the
peripherals. In particular, when using Normally Close
switch, the CRD_DET polarity must be defined during the
first cycles of the initialization.
Table 3. Card VCC, Card Clock and Card Detection Polarity Truth Table
HEXA CS PWR_ON PGM RESET A1 A0 I/O CRD_VCC CRD_CLK CRD_DET STATUS
$00 L − L L L L L 3.0 V CLOCK_IN 1/1 − H (Note 13)
$01 L − L L L L H 3.0 V CLOCK_IN 1/2 − H (Note 13)
$02 L − L L L H L 3.0 V CLOCK_IN 1/4 − H (Note 13)
$03 L − L L L H H 3.0 V CLOCK_IN 1/8 − H (Note 13)
$04 L − L L H L L 5.0 V CLOCK_IN 1/1 − H (Note 13)
$05 L − L L H L H 5.0 V CLOCK_IN 1/2 − H (Note 13)
$06 L − L L H H L 5.0 V CLOCK_IN 1/4 − H (Note 13)
$07 L − L L H H H 5.0 V CLOCK_IN 1/8 − H (Note 13)
$08 L − L H L L L − START − H (Note 13)
$09 L − L H L L H − STOP Low − H (Note 13)
$0A L − L H L H L − STOP High − H (Note 13)
$0B L − L H L H H − Reserve − H (Note 13)
$0C L − L H H L L − − Normally Open
(Note 12)
H (Note 13)
$0D L − L H H L H − − Normally Close
(Note 12)
H (Note 13)
$0E L − L H H H L − − Normally Close
(Note 12)
H (Note 13)
$0F L − L H H H H − − Normally Close
Note 12)
H (Note 13)
$10 L − H Z L L Z − − − Card Present
$12 L 1 H Z L H Z − − − DC−DC status
$14 L − H Z H L Z − − − Vbat
$16 L 1 H Z H H Z − − − CRD_VCC
9. The programmed conditions are latched upon the Chip Select (CS, pin 6) positive going transient.
10.Card clock integrity is guaranteed no spikes whatever be the frequency switching.
11. The STATUS register is not affected when the NCN6000 operates in any of the programming functions.
12.The CRD_VCC and CRD_CLK are not affected when the NCN6000 operates outside their respective decoded logic address.
13.The High Level on STATUS in registers $00 to $0F, inclusive, having being implemented to reduce current consumption but have no other
meanings.
14.At turn on, the NCN6000 is initialized with CRD_VCC = 3.0V, CLOCK_IN Ratio = 1/1, CRD_CLK = START, CRD_DET = Normally Open.
NCN6000
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14
DC−DC Converter and Card Detector Status
The NCN6000 status can be polled when CS = L. Please
consult Figures 4 and 5 for a description of input and output
signals. The status message is described in Table 4.
Note: in order to cope with a start up under low battery
condition, the Vbat OK message uses a negative logic as
depicted here below.
Table 4. Card and DC−DC Status Output
PGM A1 A0 STATUS Message
HIGH L L LOW No Card
HIGH L L HIGH Card Present
HIGH L H LOW DC−DC Converter
Overloaded
HIGH L H HIGH DC−DC Converter OK
HIGH H L LOW Vbat OK
HIGH H L HIGH Vbat Undervoltage
HIGH H H HIGH CRD_VCC OK
HIGH H H LOW CRD_VCC Undervoltage
The STATUS pin provides a feedback related to the
detection of the card, the state of the DC−DC converter, the
Vbat undervoltage and CRD_VCC undervoltage situations.
When PGM = H, the STATUS pin returns a High if a card is
detected present, a Low being asserted if there is no card
inserted. In any case, the external card is not automatically
powered up. When the external MPU asserts PWR_ON = H,
together with CS = L, the CRD_VCC supply is provided to
the card and the state of the DC−DC converter, the Vbat and
the CRD_VCC can be polled through the STATUS pin.
Card Power Supply Timing
At power up, the CRD_VCC power supply rise time
depends upon the current capability of the DC−DC
converter associated with the external inductor L1 and the
reservoir capacitor connected across CRD_VCC and
GROUND.
On the other hand, at turn off, the CRD_VCC fall time
depends upon the external reservoir capacitor and the peak
current absorbed by the internal CMOS transistor built
across CRD_VCC and GROUND. These behaviors are
depicted in Figure 6. Since these parameters have finite
values, depending upon the external constraints, the
designer must take care of these limits if the t
ON
or the t
OFF
provided by the data sheets does not meet his requirements.
Figure 6. Card Power Supply Turn ON and OFF Timing
Typical CRD_VCC Rise Time @ Cout = 10 F, V = 5.0 V Typical CRD_VCC Fall Time @ Cout = 10 F, V = 5.0 V
NCN6000
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15
Basic Operating Modes Flow Chart
The NCN6000 brings all the functions necessary to handle
data communication between a host computer and the smart
card. The built−in Chip Select pin provides a simple way to
share the same MPU bus with several card interface. On top
of that, the logic control are derived from specific pins,
avoiding the risk of mixing up the operation when the
interface is controlled by a low end microcontroller.
During the transaction operation, the external MPU takes
care of whatever is necessary to he data on the single
bidirectional I/O line. Leaving aside the DC−DC control and
associated failures, the NCN6000 does not take any further
responsibility in the data transaction.
When the chip operates in the programming mode, the
NCN6000 provide a flexible access to set up the CRD_VCC
voltage, the CRD_CLK and the CRD_DET smart card
signals.
The external microcontroller takes care of the smart card
transaction and shall handle the interface accordingly.
Figure 7. Operating Modes Flow Chart
RESET
Vbat = OK
STAND BY MODE
SELECT OPERATING MODE
PROGRAMMING
MODE
SET NCN6000
PARAMETERS
ACTIVE MODE
SEND ATR SEQUENCE
TRANSACTION MODE
END MODE
POWER DOWN SEQUENCE
IDLE MODE
FINISH
PWR_ON = H
CS = H
CS = H
PGM = H
PGM = L
CS = L
PGM = H
CS = L
LATCH NCN6000
PARAMETERS
PGM = H
CS = H
Standby Mode
The Standby Mode allows the NCN6000 to detect a card
insertion, keeping the power consumption at a minimum.
The power supply CRD_VCC is not applied to the card, until
the external controllers set PWR_ON = H with CS = L.
Standby Mode
Logic Conditions:
Card Output:
CS = H
PWR_ON = H
A0 = Z
A1 = Z
PGM = Z
I/O = Z
RESET = Z
CRD_VCC = 0 V
CRD_CLK = L
CRD_RST = L
CRD_IO = L
When a card is inserted, the internal logic filters the signal
present pin 11, then asserts the INT pin to Low if the pulse
applied to CRD_DET is longer than 150 s. The external
MPU shall run whatever is necessary to handle the card.
The INT is cleared (return to High) when a positive going
transition is asserted to either the CS or to the PWR_ON
signal logically combined with Chip Select = Low.
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NCN6000DTB

Mfr. #:
Buy NCN6000DTB
Manufacturer:
ON Semiconductor
Description:
I/O Controller Interface IC 2.7V POS/ATM Smart
Lifecycle:
New from this manufacturer.
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