NCN6000
http://onsemi.com
19
Card Detection
The card detector circuit provides a 500 k pull up
resistor to bias the CRD_DET pin, yielding a logic High
when the pin is left open (assuming a NO switch). The
internal logic associated with pin 11 provides an automatic
selection of the slope card detection, depending upon the
polarity set by the external MPU. At start up, the CRD_DET
is preset to cope with Normally Open switch. When a
Normally Close switch is used in the card socket, it is
mandatory to program the NCN6000 chip during the
initialization sequence, otherwise the system will not start if
a card was previously inserted. Table 3 gives the
programming code for such a function. The next lines
provide a typical assembler source to handle this CRD_DET
Normally Close polarity:
Smart EQU $20
LDX #$1000
LDAA #$09
STAA smart, X
; NCN6000 Physical CS Address
; Offset
; I/O = H, A0 = A1 = L, RESET = H
; Set CRD_DET = Normally Closed
Switch
The CRD_DET polarity can be updated at any time,
during the Program Mode sequence (PGM = L), but,
generally speaking, is useless since the switch does not
change during the usage of the considered module. On the
other hand, the card detection switch shall be connected
across pin 11 and ground, for any polarity selected.
The transition presents pin 11, whatever be the polarity, is
filtered out by the internal digital filter circuit, avoiding false
interrupt. In addition to the minimum internal 50 s timing,
the MPU shall provide an additional delay to cope with the
mechanical stabilization of the card interface (typically
3 ms), prior to valid the CRD_VCC supply.
When a card is inserted, the detector circuit asserts
INT = Low as depicted before. When the NCN6000 detects
a card extraction, the power down sequence is activated,
regardless of the PWR_ON state, and the INT pin is asserted
Low. It is up to the external MPU to clear this interrupt by
forcing a chip select pulse as depicted in Figure 5.
The 75 s delay represent the digital filter built−in the
NCN6000 chip being used for the characterization. Any
pulse shorter than this delay does not generate an interrupt.
However, to guarantee an interrupt will be generated, the
CRD_DET signal must be longer than 150 s as defined by
the specification.
The Chip Select pulse is generated by the external
microcontroller, the minimum pulse width being 2 s to
make sure the card is detected.
The oscillogram, Figure 11, depicts the behavior for a
Normally Open switch, the delay existing between the
interrupt negative going state and the CS being Low comes
from the particular software latency existing in this
particular MPU.
Figure 11. Card Insertion Detection and Interrupt Signals
Digital Filter Delay
INTERRUPT
Chip Select Acknowledge or Clear Interrupt
