NCN6000
http://onsemi.com
25
Clock Divider
The main purpose of the built−in clock generator is
threefold:
1. Adapts the voltage level shifter to cope with the
different voltages that might exist between the MPU
and the Smart Card.
2. Provides a frequency division to adapt the Smart
Card operating frequency from the external clock
source.
3. Controls the clock state according to the smart card
specification.
In addition, the NCN6000 adjusts the signal coming from
the microprocessor to get the Duty Cycle window as defined
by the ISO7816−3 specification.
The logic input pins A0, A1, PGM, I/O and RESET fulfill
the programming functions when both PGM and CS are
Low. The clock input stage (CLOCK_IN) can handle a
40 MHz frequency maximum, the divider being capable to
provide a 1:8 ratio. Of course, the ratio must be defined by
the engineer to cope with the Smart Card considered in a
given application and, in any case, the output clock
[CRD_CLK] shall be limited to 20 MHz maximum signal.
In order to maximize the CLOCK_IN bandwidth, this pin
has no Schmitt trigger input. The simple associated CMOS
has a Vbat/2 threshold level. In order to minimize the dI/dt
and dV/dV developed in the CRD_CLK line, the peak
current as been internally limited to 30 mA peak (typical @
CRD_VCC = 5.0 V), hence limited the rise and fall time to
10 ns typical. Consequently, the NCN6000 fulfills the
ISO7816 specification up to 10 MHz maximum, but can be
used up to 20 MHz when the final application operates in a
limited ambient temperature range.
Level Shifter
& Control
3
3
CLOCK_IN
PGM
CS
RESET
I/O
A0
A1
+3.0 V
+5.0 V
Clock & V
CC
Programming
Block
CRD_V
CC
CRD_CLK
1
2
1
2
3
3
Figure 24. Simplified Frequency Divider and Programming Functions
In order to avoid any duty cycle out of the frequency smart
card ISO7816−3 specification, the divider is synchronized
by the last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio. Consequently, the output
CRD_CLK frequency division can be delayed by eight
CLOCK_IN pulses and the microcontroller software must
take this delay into account prior to launch a new data
transaction.
