NCN6000
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22
Vbat Supply Voltage Monitoring
The built−in comparator, associated with the band gap
reference, continuously monitors the +Vbat input. During
the start up, all the NCN6000 functions are deactivated and
no data transfer can take place. When the +Vbat voltage rises
above 2.35 V (typical), the chip is activated and all the
functions becomes available. The typical behavior is
provided here after Figure 16. At this point, the internal
Power On Reset signal is activated (not accessible
externally) and all the logic signals are forced into the states
as defined by Table 3.
If the +Vbat voltage drops below 2.25 V (typical) during
the operation, the NCN6000 generate a Power Down
sequence and is forced in a no operation mode. The built−in
100 mV (typical) hysteresis avoids unstable operation when
the battery voltage slowly varies around the 2.30 V.
On the other hand, the microcontroller can read the
STATUS signal, pin 5, to control the state of the battery prior
to launch either a NCN6000 programming or an ATR
sequence (Table 4).
2.80 V
Figure 16. Typical Vbat Monitoring
Vbat
2.35 V
2.25 V
3.30 V
Vbat_OK
Vbat STATUS
Note: Drawing is not to scale and voltages are typical.
See specifications data for details.
DC−DC Converter Operation
The built−in DC−DC converter is based on a modified
boost structure to cover the full battery and card operating
voltage range. The built−in battery voltage monitor provides
an automatic system to accommodate the mode of operation
whatever be the Vbat and CRD_VCC voltages. Comparator
U3/Figure 17 tracks the two voltages and set up the
operating mode accordingly.
U2
+
U3
V
ref
+
MOS Drive
Substrat Bias
U1
PWR_ON
3 V/ 5 V
Overload
VCC_OK
R1 1R
Current Sense
20
19
18
15
17
V
bat
V
bat
L2
22 H
L
out_L
L
out_H
+
GND
CRD_VCC
C1
GND
GND
GND
V
out
_3_5
V
ref
_3/5 V
Voltage Regulation
V
bat
Q3
Q1
Q2
GND
V
bat
V
bat
/V
CC
Comparator
NMOS Gate Drive
PMOS Gate Drive
LOGIC CONTROL
GND
PWR_GND
GND
Figure 17. Basic DC−DC Structure
+
R2
R3
R4
Active Pull Down
GND
Q4
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When the input voltage Vbat is lower than the
programmed CRD_VCC, the system operates under the
boost mode, providing the voltage regulation and current
limit to the smart card. In this mode, the external inductor,
typically 22 H, stores the energy to drive the +5.0 V card
supply from the external low voltage battery. The
oscillogram, Figure 18, depicts the DC−DC behavior under
these two modes of operation.
Beside the DC−DC converter, NMOS Q4 provides a low
impedance to ground during the Power Down sequence,
yielding the 250 s maximum switch time depicted in the
data sheet.
Figure 18. DC−DC Operating Modes
Step Down Mode
CRD_VCC 5 V Step Up Mode
CRD_VCC
I
L
Ibat
DC Operating Current @ CRD_VCC = 5.0 V
0
1
2
3
4
5
6
7
8
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Vbat (V)
Ibat_op (mA)
25°C
85°C
POWER_ON
Figure 19. Typical DC Operating Current
−25°C
When the input voltage Vbat is higher than the
programmed CRD_VCC, the system operates under a step
down mode, yielding the voltage regulation and current
limit identical to the boost mode. In this case, the built−in
structure turns Off Q1 and inverts the Q2 substrate bias to
control the current flowing to the load.These operations are
fully automatic and transparent for the end user.
The High and Low limits of the current flowing into the
external inductor L1 are sensed by the operational amplifier
U1 associated with the internal shunt R1. Since this shunt
resistor is located on the hot side of the inductor, the device
reads both the charge and discharge of the inductor,
providing a clean operation of the converter.
In order to optimize the DC−DC power conversion
efficiency, it is recommended to use external inductor with
R < 2.0 .
The output capacitor C1 stores the energy coming from the
converter and smooths the CRD_VCC voltage applied to the
external card. At this point, care must be observed, beside the
micro farad value, to select the right type of capacitor.
According to the capacitors manufacturers, the internal ESR
can range from a low 10 m to more than 3.0 , thus yielding
high losses during the DC−DC operation, depending upon the
technology used to build the capacitor.
The standard electrolytic capacitors have the low cost
advantage for a relative high micro farad value, but have
poor tolerance, high leakage current and high ESR.
The tantalum type brings much lower leakage current
together with high capacity value per volume, but cost can
be an issue and ESR is rarely better than 500 m.
The new ceramic type have a very low leakage together
with ESR in the 50 m range, but value above 10 F are
relatively rare. Moreover, depending upon the low cost
ceramic material used to build these capacitors, the thermal
coefficient can be very bad, as depicted in Figure 20. The
X7R type is highly recommended to achieve low voltage
ripple.
Figure 20. Typical Y7R Ceramic Type Value as a
Function of the Temperature.
100%
−25°C +25°C +85°C
15%
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Based on the experiments carried out during the
NCN6000 characterization, the best comprise, at time of
printing this document, is to use two
6.8F/10 V/Ceramic/X7R capacitor in parallel to achieve
the CRD_VCC filtering. The ESR will not extend 50 m
over the temperature range and the combination of standard
parts provide an acceptable –20% to +20% tolerance,
together with a low cost. Obviously, the capacitor must be
SMD type to achieve the extremely low ESR and ESL
necessary for this application. Figure 21 illustrates the
CRD_VCC ripple observed in the NCN6000 demo board
depending upon the type of capacitor used to filter the output
voltage.
Table 5. Ceramic/Electrolytic Capacitors Comparison
Manufacturers Type/Series Format Max Value Tolerance Typ. Z @ 500 kHz
MURATA CERAMIC/GRM225 0805
10 F/6.3 V
+80%/−20%
30 m
VISHAY Tantalum/594C/593C
10 F/16 V 450 m
VISHAY Electrolytic/94SV
10 F/10 V
−20%/+20%
400 m
Electrolytic Low Cost
10 F/10 V
−35%/+50%
2.0
Top Trace = Electrolytic or Tantalum 10 F
Bottom Trace = X7R 10 F ceramic
The high ripple pulse across CRD_VCC is the consequence
of the large ESR of the electrolytic capacitor.
Figure 21. CRD_VCC Ripple as a Function of the Capacitor Technology
C= 10 F
Electrolytic or Tantalum
C= 10 F
Ceramic
NOTES: Rload = 100 , Vbat = 5.0 V, CRD_VCC = 5.0 V
Cout = 10 F/X7R, CRD_CLK = Stop High
Figure 22. External Capacitor Current Charge and
CRD_VCC Voltage Ripple.
Figure 23. CRD_VCC Voltage Ripple

NCN6000DTB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
I/O Controller Interface IC 2.7V POS/ATM Smart
Lifecycle:
New from this manufacturer.
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