2©2016 Integrated Device Technology, Inc Revision C January 27, 2016
894D115I-04 Data Sheet
Functional Description
The 894D115I-04 is designed to extract the clock from a
NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input
data signals. The output signals are the recovered clock and
retimed data signals. The device contains an integrated PLL for
clock generation and to lock the output clock to the input data
stream. The PLL attempts to lock to the reference clock input
(REF_CLK) in absence of the serial data stream or if it is forced to
by the control inputs LOCK_REFN or SD. The output clock
frequency is controlled by the STS12 input. The output frequency
is 622.08MHz in STM-4/OC-12/STS-12 mode and 155.52MHz in
STM-1/OC-3/STS-3 mode.
The 894D115I-04 will maintain an output (CLK_OUT/ nCLK_OUT)
frequency deviation of less than ±500ppm with respect to the
REF_CLK reference frequency in a loss of signal state (LOS).
During the LOS state, the data outputs (DATA_OUT/
nDATA_OUT) are held at logic low state. An LOS state of the
894D115I-04 is given when BYPASS is set to the logic low state
and either one of the SD or LOCK_REFN inputs are at a logic low
state.
This will enable the use of the SD (signal detect) and the
LOCK_REFN (lock-to-reference) inputs to accept loss of signal
status information from electro-optical receivers. Please refer to
Figure 1, “Signal Detect/PLL Bypass Operation Control Diagram”,
for details.
The lock detect output (LOCK_DET) can be used to monitor the
operating state of the clock/data recovery circuit. LOCK_DET is
set to logic low level when the internal oscillator of the PLL and
the reference clock (REF_CLK) deviate from each other by more
than 500ppm, or when the CDR is forced to lock the REF_CLK
input by the LOCK_REFN or SD control input. LOCK_DET is set
to high when the PLL is locked to the input data stream and
indicates valid clock and data output signals.
The BYPASS pin should be set to logic low state in all
applications. BYPASS set to logic high state is used during factory
test. In BYPASS mode (BYPASS and STS12 are at logic high
state), the internal PLL is bypassed and the inverted REF_CLK
input signal is output at CLK_OUT/nCLK_OUT.
Figure 1. Signal Detect/PLL BYPASS Operation Control Diagram
LOS
(on-chip)
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
STS12
BYPASS
DATA_IN
nDATA_IN
PLL Clock
(on-chip)
SD
LOCK_REFN
REF_CLK
0
1
Pullup/Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
