1337GDVGI Datasheet 1337GDVGI8, 1337GDVGI, 1337GDCGI | P10-P12

IDT1337G

REAL-TIME CLOCK WITH I

C SERIAL INTERFACE RTC

IDT®

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C SERIAL INTERFACE 10

IDT1337G REV M 073013

C Serial Data Bus

The IDT1337G supports the I

C bus protocol. A device that

sends data onto the bus is defined as a transmitter and a

device receiving data as a receiver. The device that controls

the message is called a master. The devices that are

controlled by the master are referred to as slaves. A master

device that generates the serial clock (SCL), controls the

bus access, and generates the START and STOP conditions

must control the bus. The IDT1337G operates as a slave on

the I

C bus. Within the bus specifications, a standard mode

(100 kHz maximum clock rate) and a fast mode (400 kHz

maximum clock rate) are defined. The IDT1337G works in

both modes. Connections to the bus are made via the

open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (see the “Data

Transfer on I

C Serial Bus” figure):

• Data transfer may be initiated only when the bus is not

busy.

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH are interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line,

from HIGH to LOW, while the clock is HIGH, defines a

START condition.

Stop data transfer: A change in the state of the data line,

from LOW to HIGH, while the clock line is HIGH, defines the

STOP condition.

Data valid: The state of the data line represents valid data

when, after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal. The data on

the line must be changed during the LOW period of the clock

signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and

terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions are

not limited, and are determined by the master device. The

information is transferred byte-wise and each receiver

acknowledges with a ninth bit.

Acknowledge: Each receiving device, when addressed, is

obliged to generate an acknowledge after the reception of

each byte. The master device must generate an extra clock

pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line

during the acknowledge clock pulse in such a way that the

SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse. Of course, setup and hold

times must be taken into account. A master must signal an

end of data to the slave by not generating an acknowledge

bit on the last byte that has been clocked out of the slave. In

this case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

IDT1337G

REAL-TIME CLOCK WITH I

C SERIAL INTERFACE RTC

IDT®

REAL-TIME CLOCK WITH I

C SERIAL INTERFACE 11

IDT1337G REV M 073013

Data Transfer on I

C Serial Bus

Depending upon the state of the R/W bit, two types of data

transfer are possible:

1) Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The

slave returns an acknowledge bit after each received byte.

Data is transferred with the most significant bit (MSB) first.

2) Data transfer from a slave transmitter to a master

receiver. The first byte (the slave address) is transmitted by

the master. The slave then returns an acknowledge bit,

followed by the slave transmitting a number of data bytes.

The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received

byte, a “not acknowledge” is returned. The master device

generates all of the serial clock pulses and the START and

STOP conditions. A transfer is ended with a STOP condition

or with a repeated START condition. Since a repeated

START condition is also the beginning of the next serial

transfer, the bus is not released. Data is transferred with the

most significant bit (MSB) first.

The IDT1337G can operate in the following two modes:

1) Slave Receiver Mode (Write Mode): Serial data and

clock are received through SDA and SCL. After each byte is

received an acknowledge bit is transmitted. START and

STOP conditions are recognized as the beginning and end

of a serial transfer. Address recognition is performed by

hardware after reception of the slave address and direction

bit (see the “Data Write–Slave Receiver Mode” figure). The

slave address byte is the first byte received after the START

condition is generated by the master. The slave address

byte contains the 7-bit IDT1337G address, which is

1101000, followed by the direction bit (R/W

), which is 0 for a

write. After receiving and decoding the slave address byte

the device outputs an acknowledge on the SDA line. After

the IDT1337G acknowledges the slave address + write bit,

the master transmits a register address to the IDT1337G.

This sets the register pointer on the IDT1337G. The master

may then transmit zero or more bytes of data, with the

IDT1337G acknowledging each byte received. The address

pointer increments after each data byte is transferred. The

master generates a STOP condition to terminate the data

write.

2) Slave Transmitter Mode (Read Mode): The first byte is

received and handled as in the slave receiver mode.

However, in this mode, the direction bit indicates that the

transfer direction is reversed. Serial data is transmitted on

SDA by the IDT1337G while the serial clock is input on SCL.

START and STOP conditions are recognized as the

beginning and end of a serial transfer (see the “Data

Read–Slave Transmitter Mode” figure). The slave address

byte is the first byte received after the START condition is

generated by the master. The slave address byte contains

the 7-bit IDT1337G address, which is 1101000, followed by

the direction bit (R/W

), which is 1 for a read. After receiving

and decoding the slave address byte the slave outputs an

acknowledge on the SDA line. The IDT1337G then begins

to transmit data starting with the register address pointed to

IDT1337G

REAL-TIME CLOCK WITH I

C SERIAL INTERFACE RTC

IDT®

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IDT1337G REV M 073013

by the register pointer. If the register pointer is not written to

before the initiation of a read mode the first address that is

read is the last one stored in the register pointer. The

IDT1337G must receive a “not acknowledge” to end a read.

Data Write – Slave Receiver Mode

Data Read (from current Pointer location) – Slave Transmitter Mode

Data Read (Write Pointer, then Read) – Slave Receive and Transmit

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1337GDVGI

Mfr. #:

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Manufacturer:

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Description:

Real Time Clock Real Time Clock

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