IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE RTC
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 16
IDT1337G REV M 073013
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA
, and SQW/INTB.
Note 4: I
CCA
—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I
2
C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 <
VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHMIN
of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+
t
SU:DAT
= 1000 + 250 = 1250 ns before the SCL line is released.
Note 14: C
B
—total capacitance of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
