IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE RTC
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 4
IDT1337G REV M 073013
Typical Operating Circuit
Detailed Description
Communications to and from the IDT1337G occur serially
over an I
2
C bus. The IDT1337G operates as a slave device
on the serial bus. Access is obtained by implementing a
START condition and providing a device identification code,
followed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The device
is fully accessible through the I
2
C interface whenever VCC
is between 5.5 V and 1.8 V. I
2
C operation is not guaranteed
when VCC is below 1.8 V. The IDT1337G maintains the time
and date when VCC is as low as 1.3 V.
The following sections discuss in detail the Oscillator block,
Clock/Calendar Register Block and Serial I
2
C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1337G RTC are:
Recommended Load Capacitance
Crystal Effective Series Resistance (ESR)
Frequency Tolerance
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
CPU
X1 X2
V
CC
SQW/INTB
INTA
GND
SDA
SCL
CRYSTAL
IDT1337G
V
CC
2k
2k
V
CC
V
CC
10k
10k
IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE RTC
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 5
IDT1337G REV M 073013
Note: IDT1337CSRI integrates a standard 32.768 kHz
crystal in the package and contributes an additional
frequency error of 10ppm at nominal
V
CC
(+3.3 V) and
T
A
=+25°C.
ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
Frequency Tolerance
The frequency tolerance for 32 kHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1337G
typically have a frequency tolerance of +/-20ppm at +25°C.
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
PCB Design Consideration
Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
PCB Layout
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32 KHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
Parameter Symbol Min Typ Max Units
Nominal Freq. f
O
32.768 kHz
Series Resistance ESR 80 k
Load Capacitance C
L
7pF
IDT1337G
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE RTC
IDT®
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 6
IDT1337G REV M 073013
Address Map
Table 2 (Timekeeper Registers) shows the address map for the IDT1337G registers. During a multibyte access, when the
address pointer reaches the end of the register space (0Fh), it wraps around to location 00h. On an I
2
C START, STOP, or
address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read
the registers in case of an update of the main registers during a read.
Table 1. Timekeeper Registers
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC falls below the V
CCT
min
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Range
00h 0 10 seconds Seconds Seconds 00 - 59
01h 0 10 minutes Minutes Minutes 00 - 59
02h 0 12/24
AM/PM
10 hour Hour Hours
1 - 12 +
AM/PM
00 - 23
10 hour
03h00000 Day Day 1 - 7
04h 0 0 10 date Date Date 01 - 31
05h Century 0 0 10 month Month Month/Century 01 - 12 +
Century
06h 10 year Year Year 00 - 99
07h A1M1 10 seconds Seconds Alarm 1
Seconds
00 - 59
08h A1M2 10 minutes Minutes Alarm 1
Minutes
00 - 59
09h A1M3 12/24
AM/PM
10 hour Hour Alarm 1 Hours
1 - 12 +
AM/PM
00 - 23
10 hour
0Ah A1M4 DY/DT
10 date
Day, Alarm 1 Day 1 - 7
Date Alarm 1 Date 1 - 31
0Bh A2M2 10 minutes Minutes Alarm 2
Minutes
00 - 59
0Ch A2M3 12/24
AM/PM
10 hour Hour Alarm 2 Hours
1 - 12 +
AM/PM
00 - 23
10 hour
0Dh A2M4 DY/DT
10 date
Day, Alarm 2 Day 1 - 7
Date Alarm 2 Date 1 - 31
0Eh EOSC
0 0 RS2 RS1 INTCN A2IE A1IE Control
0FhOSF00000A2FA1FStatus

1337GDVGI

Mfr. #:
Manufacturer:
IDT
Description:
Real Time Clock Real Time Clock
Lifecycle:
New from this manufacturer.
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