ADG1406/ADG1407 Data Sheet
Rev. C | Page 16 of 20
1.2
1.0
0.8
0.6
0.4
0.2
0
02 8 14 20
07419-024
THD + N (%)
FREQUENCY (kHz)
4101661218
V
DD
= +5V
V
SS
= –5V
T
A
= 25°C
R
L
=110
V
S
= 10V p-p
V
S
= 5V p-p
V
S
= 2.5V p-p
Figure 25. THD + N vs. Frequency, 5 V Dual Supply
0
–20
–40
–60
–80
–100
–120
100
10M1k
ACPSRR (dB)
10k 100k
1M
FREQUENCY (Hz)
07419-025
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
V p-p = 0.63V
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
ON SUPPLIES
Figure 26. ACPSRR vs. Frequency
Data Sheet ADG1406/ADG1407
Rev. C | Page 17 of 20
TERMINOLOGY
R
ON
Ohmic resistance between the D and S terminals.
ΔR
ON
Difference between the R
ON
of any two channels.
R
FLAT(ON)
Flatness is defined as the difference between the maximum
and minimum value of on resistance as measured.
I
S
(Off)
Source leakage current when the switch is off.
I
D
(Off)
Drain leakage current when the switch is off.
I
D
, I
S
(On)
Channel leakage current when the switch is on.
V
D
, V
S
Analog voltage on Terminal D and Terminal S.
C
S
(Off)
Channel input capacitance for the off condition.
C
D
(Off)
Channel output capacitance for the off condition.
C
D
, C
S
(On)
On switch capacitance.
C
IN
Digital input capacitance.
t
ON
(EN)
Delay time between the 50% and 90% points of the digital input
and the switch on condition.
t
OFF
(EN)
Delay time between the 50% and 90% points of the digital input
and the switch off condition.
t
TRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
t
BBM
Off time measured between the 80% points of the switches
when switching from one address state to another.
V
INL
Maximum input voltage for Logic 0.
V
INH
Minimum input voltage for Logic 1.
I
INL
, I
INH
Input current of the digital input.
I
DD
Positive supply current.
I
SS
Negative supply current.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Total Harmonic Distortion Plus Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
Measures the ability of a device to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modu-
lated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is
the ACPSRR.
ADG1406/ADG1407 Data Sheet
Rev. C | Page 18 of 20
TEST CIRCUITS
I
DS
SD
V
S
V
07419-125
Figure 27. On Resistance
SD
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
07419-026
Figure 28. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
07419-027
Figure 29. On Leakage
3V
0V
OUTPUT
t
r
< 20ns
t
f
< 20ns
ADDRESS
DRIVE (V
IN
)
t
TRANSITION
t
TRANSITION
50% 50%
90%
90%
OUTPUT
ADG1406
1
50
300
GND
S1
S2 TO S15
S16
D
35pF
V
IN
2.4V EN
DD
SS
V
DD
V
SS
V
S1
V
S16
1
SIMILAR CONNECTION FOR ADG1407.
A0
A2
A1
A3
07419-028
Figure 30. Address to Output Switching Times, t
TRANSITION
3V
0V
OUTPUT
80% 80%
A
DDRESS
DRIVE (V
IN
)
t
BBM
OUTPUT
ADG1406
1
50
300
GND
S1
S2 TO S15
S16
D
35pF
V
IN
2.4V EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG1407.
A0
A2
A1
A3
07419-029
Figure 31. Break-Before-Make Delay, t
BBM
3V
0V
OUTPUT
50% 50%
t
OFF
(EN)
t
ON
(EN)
0.9V
OUT
0.9V
OUT
ENABLE
DRIVE (V
IN
)
OUTPUT
ADG1406
1
300
GND
S1
S2 TO S16
D
35pF
50
V
IN
EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG1407.
A0
A2
A1
A3
0
7419-030
Figure 32. Enable Delay, t
ON
(EN), t
OFF
(EN)

ADG1407BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 110MHz 9.5 Ohm iCMOS
Lifecycle:
New from this manufacturer.
Delivery:
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