Electrical specifications VN5160S-E
10/31 Doc ID 13493 Rev 5
Table 8. Status pin (V
SD
=0)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
Status low output voltage I
STAT
= 1.6 mA, V
SD
= 0V 0.5 V
I
LSTAT
Status leakage current
Normal operation or V
SD
= 5V,
V
STAT
= 5V
10 µA
C
STAT
Status pin input
capacitance
Normal operation or V
SD
=5V,
V
STAT
= 5V
100 pF
V
SCL
Status clamp voltage
I
STAT
= 1mA
I
STAT
= - 1mA
5.5
-0.7
7V
V
Table 9. Protection
(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit current
V
CC
= 13V
5V<V
CC
<36V
3.8 5.4 7.5
7.5
A
A
I
limL
Short circuit current during
thermal cycling
V
CC
= 13V; T
R
<T
j
<T
TSD
2A
T
TSD
Shutdown temperature 150 175 200 °C
T
R
Reset temperature
T
RS
+ 1
T
RS
+ 5 °C
T
RS
Thermal reset of STATUS 135 °C
T
HYST
Thermal hysteresis (T
TSD
-T
R
)
C
t
SDL
Status delay in overload
conditions
T
j
>T
TSD
20 µs
V
DEMAG
Turn-off output voltage
clamp
I
OUT
=150mA; V
IN
=0 V
CC
-41 V
CC
-46 V
CC
-52 V
V
ON
Output voltage drop
limitation
I
OUT
= 0.03A;
T
j
=-40°C...+150°C
(see Figure 5)
25 mV
VN5160S-E Electrical specifications
Doc ID 13493 Rev 5 11/31
Table 10. Openload detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
OL
Openload on-state
detection threshold
V
IN
= 5V, 8V<V
CC
<18V 10
See
Figure 19
40 mA
t
DOL(on)
Openload on-state
detection delay
I
OUT
= 0A, V
CC
=13V
(see Figure 4)
200 µs
t
POL
Delay between INPUT falling
edge and STATUS rising
edge in openload condition
I
OUT
= 0A (see Figure 4) 200 500 1000 µs
V
OL
Openload off-state voltage
detection threshold
V
IN
= 0V, 8V<V
CC
<16V 2
See
Figure 20
4V
t
DSTKON
Output short circuit to V
cc
detection delay at turn-off
(see Figure 4) 180 t
POL
µs
Table 11. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level voltage 0.9 V
I
IL
Low level input current V
IN
= 0.9V 1 µA
V
IH
Input high level voltage 2.1 V
I
IH
High level input current V
IN
= 2.1V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
STAT_DIS low level voltage 0.9 V
I
SDL
Low level STAT_DIS current V
CSD
= 0.9V 1 µA
V
SDH
STAT_DIS high level voltage 2.1 V
I
SDH
High level STAT_DIS current V
CSD
= 2.1V 10 µA
V
SD(hyst)
STAT_DIS hysteresis voltage 0.25 V
V
SDCL
STAT_DIS clamp voltage
I
SD
= 1mA
I
SD
= -1mA
5.5
-0.7
7V
V
Electrical specifications VN5160S-E
12/31 Doc ID 13493 Rev 5
Figure 4. Status timings
Figure 5. Output voltage drop limitation
V
IN
V
STAT
t
POL
OPEN LOAD STATUS TIMING (without external pull-up)
I
OUT
< I
OL
V
OUT
< V
OL
t
DOL(on)
V
IN
V
STAT
OPEN LOAD STATUS TIMING (with external pull-up)
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
V
IN
V
STAT
OVER TEMP STATUS TIMING
t
SDL
t
SDL
T
j
> T
TSD
V
IN
V
STAT
t
DSTKON
OUTPUT STUCK TO Vcc
I
OUT
> I
OL
V
OUT
> V
OL
t
DOL(on)
V
on
I
out
V
cc
-V
out
T
j
=150
o
C
T
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)

VN5160S-E

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Gate Drivers Sngl Ch HiSide Drivr
Lifecycle:
New from this manufacturer.
Delivery:
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