LTC3634
15
3634fc
For more information www.linear.com/LTC3034
When SW1 and SW2 operate 180° out-of-phase, the worst-
case input RMS current occurs when the V
TT
supply is
sinking current and V
DDQ
is sourcing the same amount of
current. Knowing that V
OUT2
= one-half V
OUT1
in the DDR
application, the input RMS current in this case is given by:
I
RMS
= I
OUT(MAX)
D1 1.5−
D1
4
for D1 < 0.5
I
RMS
= I
OUT(MAX)
1−
3
4
D1 for D1 > 0.5
where D1 is the duty cycle of channel 1 (V
DDQ
supply).
These equations show that maximum I
RMS
occurs at
50% duty cycle (V
IN
= 2 • V
OUT1
). This simple worst-case
condition may be used for design as deviations in duty
cycle do not offer significant relief. Note that ripple current
ratings from capacitor manufacturers are often based on
only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
Even though the LTC3634 design includes an overvoltage
protection circuit, care must always be taken to ensure
input voltage transients do not pose an overvoltage haz-
ard to the part.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, ΔV
OUT
, is
approximated by:
∆V
OUT
< ∆I
L
ESR+
1
8 • f •C
OUT
When using low-ESR ceramic capacitors, it is more use-
ful to choose the output capacitor value to fulfill a charge
storage requirement. During a load step, the output capacitor
APPLICATIONS INFORMATION
must instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, three to four cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
V
DROOP
, is usually about three times the linear drop of
the first cycle, provided the loop crossover frequency is
maximized. Thus, a good place to start is with the output
capacitor size of approximately:
C
OUT
≈
OUT
f • V
DROOP
Though this equation provides a good approximation, more
capacitance may be required depending on the duty cycle
and load step requirements. The actual V
DROOP
should be
verified by applying a load step to the output.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are available
in small case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, due to the self-resonant and high-
Q characteristics of some types of ceramic capacitors,
care must be taken when these capacitors are used at
the input. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
V
IN
input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part. For
a more detailed discussion, refer to Application Note 88.
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
