LTC3634
22
3634fc
For more information www.linear.com/LTC3034
APPLICATIONS INFORMATION
be 1MHz • 2.3nC = 2.3mA, and the total I
Q
of both chan-
nels is 1.3mA (see the Electrical Characteristics section).
Therefore, the total power dissipated by both regulators is:
P
D
= I
OUT1
( )
2
R
SW1
+ I
OUT2
( )
2
R
SW2
+ V
IN
I
GATECHG
+I
Q
( )
P
D
=(2A)
2
0.0848+(2A)
2
0.0799
+12V 2.3mA 2
( )
+1.3mA
= 0.730W
The QFN 4mm × 5mm package junction-to-ambient thermal
resistance, θ
JA
, is around 43°C/W. Therefore, the junction
temperature of the regulator operating in a 70°C ambient
temperature is approximately:
T
J
= 0.730W • 43°C/W + 70°C = 101°C
which is below the maximum junction temperature of
125°C. With higher ambient temperatures, a heat sink or
cooling fan should be considered to drop the junction-to-
ambient thermal resistance. Alternatively, the exposed pad
TSSOP package may be a better choice for high power
applications, since it has better thermal properties than
the QFN package.
Remembering that the above junction temperature is ob-
tained from a R
DS(ON)
at 70°C, we might recalculate the
junction temperature based on a higher R
DS(ON)
since it
increases with temperature. Redoing the calculation as-
suming that R
SW
increased 12% at 101°C yields a new
junction temperature of 105°C.
Figure 8 is a temperature derating curve based on the
DC1708 demo board (QFN package). It can be used as
a guideline to estimate the maximum allowable ambient
temperature for given DC load currents in order to avoid
exceeding the maximum operating junction temperature
of 125°C.
Junction Temperature Measurement
The junction-to-ambient thermal resistance will vary de-
pending on the size and amount of heat sinking copper
on the PCB board where the part is mounted, as well as
the amount of air flow on the device. In order to properly
evaluate this thermal resistance, the junction temperature
needs to be measured. A clever way to measure the junction
Figure 8. Temperature Derating Curve for DC1708 Demo Circuit
temperature directly is to use the internal junction diode
on one of the PGOOD pins to measure its diode voltage
change based on ambient temperature change.
First remove any external passive component on the PGOOD
pin, then pull out 100μA from the PGOOD pin to turn on
its internal junction diode and bias the PGOOD pin to a
negative voltage. With no output current load, measure the
PGOOD voltage at an ambient temperature of 25°C, 75°C
and 125°C to establish a slope relationship between the
voltage on PGOOD and ambient temperature. Once this
slope is established, then the junction temperature rise can
be measured as a function of power loss in the package
with corresponding output load current. Although making
this measurement with this method does violate absolute
maximum voltage ratings on the PGOOD pin, the applied
power is so low that there should be no significant risk
of damaging the device.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3634. Check the following in your layout:
1. Do the input capacitors connect to the V
IN
and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2. The output capacitor, C
OUT
, and inductor L should be
closely connected to minimize loss. The () plate of
0
CHANNEL 1 LOAD CURRENT (A)
0.5
1.0
1.5
2.0
3.0
2.5
50
125
3634 F08
0
3.5
25 75 100
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
CH2 LOAD = 0A
CH2 LOAD = 1A
CH2 LOAD = 2A
CH2 LOAD = 3A
LTC3634
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3634fc
For more information www.linear.com/LTC3034
C
OUT
should be closely connected to both PGND and
the (–) plate of C
IN
.
3. The resistive divider, (e.g. R1 and R2 in Figure 1) must
be connected between the (+) plate of C
OUT
and a
ground line terminated near SGND. The feedback signal
V
FB
should be routed away from noisy components
and traces, such as the SW line, and its trace length
should be minimized. In addition, the R
T
resistor and
loop compensation components should be terminated
to SGND.
4. Keep sensitive components away from the SW pin. The
R
T
resistor, the compensation components, the feedback
resistors, and the INTV
CC
bypass capacitor should all
be routed away from the SW trace and the inductor L.
5. A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND). Refer to Figures 10
and 11 for board layout examples.
Design Example
As a design example, consider using the LTC3634 (as
shown in Figure 1) to power DDR2 SDRAM with the fol-
lowing specifications: V
IN(MAX)
= 13.2V, I
OUT(MAX)
= ±2A,
f = 1MHz, V
DROOP(VDDQ)
< 60mV, V
DROOP(VTT
) < 30mV.
The following discussion will use equations from the
previous sections.
First, the correct R
T
resistor value for 1MHz switching
frequency must be chosen. Based on previous discus-
sions, R
T
is calculated to be
R
T
=
3.2E
11
f
= 320k
The closest standard value is 324k.
Next, select values for R1 and R2 to set channel 1 (V
DDQ
)
to be 1.8V for DDR2 SDRAM. Choosing R1 to be 12.1k,
R2 is calculated to be:
R2= 12.1k
1.8V
0.6V
1
= 24.2k
The closest standard value is 24.3k. Tying VDDQIN to
V
OUT1
sets V
OUT2
to be half of V
OUT1
.
Next, we can pick inductor values for both the V
DDQ
and
V
TT
outputs. Choosing inductor current ripple to be 1A
at maximum V
IN
:
L1=
1.8V
1MHz 1A
1
1.8V
13.2V
=1.55µH
L2 =
0.9V
1MHz 1A
1
0.9V
13.2V
= 0.838µH
Standard values of 1.5μH and 0.82µH should be used.
Ceramic caps will be used for C
OUT
and will be selected
based on the charge storage requirement. Assuming a
worst case 4A load step (–2A to 2A):
C
OUT1
3 4A
1MHz 60mV
= 200µF
C
OUT2
3 4A
1MHz 30mV
= 400µF
Lastly, we will choose compensation components. Choos-
ing the crossover frequency f
C
= 50kHz:
R
COMP1
=
2π 50kHz 200µF
1m
1
7
1
1.8V
0.6V
= 27k
R
COMP2
=
2π 50kHz 400µF
1m
1
7
1
0.9V
0.9V
=18k
Choosing the zero frequency to be 10kHz yields C
COMP1
=
589pF and C
COMP2
= 884pF. The closest standard values
for the compensation components are 26.7k, 18k, 560pF
and 910pF, respectively.
The final circuit is shown in Figure 9.
APPLICATIONS INFORMATION
LTC3634
24
3634fc
For more information www.linear.com/LTC3034
Figure 9. Design Example Circuit
APPLICATIONS INFORMATION
RUN1
RUN2
RT
INTV
CC
PHMODE
MODE/SYNC
ITH1
ITH2
LTC3634
3634 F09
L1
1.5µH
0.1µF
0.01µF
0.1µF
R1
12.1k
R2
24.3k
PGNDSGND
BOOST1
SW1
V
ON1
VDDQIN
V
FB1
BOOST2
SW2
V
FB2
V
ON2
VTTR
V
IN1
V
IN
3.6V TO 15V
V
IN2
L2
0.82µH
R3
324k
C
OUT2
100µF
×4
C
OUT1
100µF
×2
V
DDQ
1.8V
V
TT
0.9V
V
REF
0.9V
C5
10pF
R
COMP1
26.7k
C
COMP1
560pF
R
COMP2
18k
C
COMP2
910pF
C2
2.2µF
C1
47µF
×2
C4
10pF
Figure 10. Example of Power Component Layout
for QFN Package
Figure 11. Example of Power Component Layout
for TSSOP Package
SW1
SW2
VIAS TO GROUND
PLANE
VIAS TO GROUND
PLANE
VIAS TO GROUND
PLANE
VIA TO BOOST2
VIA TO BOOST1
VIA TO V
ON2
AND V
FB2
(NOT SHOWN)
VIA TO V
ON1
AND R2 (NOT SHOWN)
V
OUT2
V
OUT1
SGND (TO NONPOWER
COMPONENTS)
3634 F11
L1
L2
C
OUT2
C
OUT1
C
IN
C
IN
GND
GND
V
IN
C
BOOST1
C
BOOST2
SW2
C
BOOST2
C
BOOST1
SW1
VIAS TO GROUND
PLANE
VIAS TO GROUND
PLANE
VIAS TO GROUND
PLANE
VIA TO BOOST1
VIA TO BOOST2
VIA TO V
ON2
AND V
FB2
(NOT SHOWN)
VIA TO V
ON1
/R2 (NOT SHOWN)
V
OUT2
GND
V
IN
GND
V
OUT1
SGND (TO NONPOWER
COMPONENTS)
3634 F10
C
OUT2
C
IN
C
IN
C
OUT1
L2
L1

LTC3634IFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 15V Dual 3A Monolithic Step Down Regulator for DDR Power
Lifecycle:
New from this manufacturer.
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