2-Channel, 2.35 V to 5.25 V
250 kSPS, 10-/12-Bit ADCs
AD7911/AD7921
Rev. A
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FEATURES
Fast throughput rate: 250 kSPS
Specified for V
DD
of 2.35 V to 5.25 V
Low power:
4 mW typ at 250 kSPS with 3 V supplies
13.5 mW typ at 250 kSPS with 5 V supplies
Wide input bandwidth:
71 dB minimum SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 μA maximum
8-lead TSOT package
8-lead MSOP package
APPLICATIONS
Battery-powered systems:
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The AD7911/AD7921
1
are 10-bit and 12-bit, high speed, low
power, 2-channel successive approximation ADCs, respectively.
The parts operate from a single 2.35 V to 5.25 V power supply
and feature throughput rates of up to 250 kSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier,
which can handle input frequencies in excess of 6 MHz. The
conversion process and data acquisition are controlled using
CS
and the serial clock, allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of
CS
, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The channel to be converted is selected through the DIN pin,
and the mode of operation is controlled by
CS
. The serial data
stream from the DOUT pin has a channel identifier bit, which
provides information about the converted channel.
1
Protected by U.S. Patent Number 6,681,332.
FUNCTIONAL BLOCK DIAGRAM
04350-0-001
T/H
CONTROL LOGIC
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
GND
V
DD
AD7911/AD7921
V
IN0
V
IN1
SCLK
DOUT
CS
DIN
MUX
Figure 1.
The AD7911/AD7921 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from V
DD
, thereby
allowing the widest dynamic input range to the ADC. The
analog input range for the part, therefore, is 0 to V
DD
. The
conversion rate is determined by the SCLK signal.
PRODUCT HIGHLIGHTS
1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package.
2. Low power consumption.
3. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock;
conversion time is reduced when the serial clock speed is
increased. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Average power consumption is reduced when the power-
down mode is used while not converting. Current
consumption is 1 μA maximum and 50 nA typically when
in power-down mode.
4. Reference derived from the power supply.
5. No pipeline delay.
The parts feature a standard successive approximation
ADC with accurate control of the sampling instant via a
CS
input and once-off conversion control.
