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AD7921ARMZ

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AD7911/AD7921
Rev. A | Page 7 of 28
TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
V
DD
= 2.35 V to 5.25 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
1
10 kHz min
2
5 MHz max
t
CONVERT
16 × t
SCLK
AD7921
14 × t
SCLK
AD7911
t
QUIET
30 ns min Minimum quiet time required between bus relinquish and start of next conversion
t
1
15 ns min
Minimum CS
pulse width
t
2
10 ns min
CS
to SCLK setup time
t
3
3
30 ns max
Delay from CS
until DOUT three-state is disabled
t
4
3
45 ns max DOUT access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
4
10 ns min SCLK to DOUT valid hold time
t
8
5 ns min DIN setup time prior to SCLK falling edge
t
9
6 ns min DIN hold time after SCLK falling edge
t
10
5
30 ns max SCLK falling edge to DOUT three-state
10 ns min
SCLK falling edge to DOUT three-state
t
POWER-UP
6
1 μs max Power-up time from full power-down
1
Mark/space ratio for SCLK input is 40/60 to 60/40.
2
Minimum f
SCLK
at which specifications are guaranteed.
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross V
IH
or V
IL
voltage.
4
Measured with a 50 pF load capacitor.
5
T
10
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
See the Power-Up Time section.
TIMING DIAGRAMS
04350-0-002
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
04350-0-003
SCLK
V
IH
V
IL
DOUT
t
4
Figure 3. Access Time after SCLK Falling Edge
04350-0-004
SCLK
V
IH
V
IL
DOUT
t
7
Figure 4. Hold Time after SCLK Falling Edge
04350-0-005
SCLK
1.6V
DOUT
t
10
Figure 5. SCLK Falling Edge to DOUT Three-State
AD7911/AD7921
Rev. A | Page 8 of 28
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1
As shown in Figure 7, when f
SCLK
= 5 MHz and the throughput is
250 kSPS, the cycle time is
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 4 μs
With t
2
= 10 ns minimum, then t
ACQ
is 1.49 μs, which satisfies
the requirement of 290 ns for t
ACQ
.
In Figure 7, t
ACQ
is comprised of 2.5(1/f
SCLK
) + t
10
+ t
QUIET
, where
t
10
= 30 ns maximum. This allows a value of 960 ns for t
QUIET
,
satisfying the minimum requirement of 30 ns.
Timing Example 2
The AD7921 can also operate with slower clock frequencies. As
shown in Figure 7, when f
SCLK
= 2 MHz and the throughput rate
is 100 KSPS, the cycle time is
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 10 μs
With t
2
= 10 ns minimum, then t
ACQ
is 3.74 μs, which satisfies
the requirement of 290 ns for t
ACQ
.
In Figure 7, t
ACQ
is comprised of 2.5(1/f
SCLK
) + t
10
+ t
QUIET
, where
t
10
= 30 ns maximum. This allows a value of 2.46 μs for t
QUIET
,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum t
QUIET
between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
04350-0-006
ZERO
X
12345 13141516
X CHN X X X X XX
CHN X DB11 DB10 DB2 DB1 DB0Z
t
2
t
6
t
4
t
8
t
9
t
3
t
7
t
5
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE
THREE-STATE
DIN
B
Figure 6. AD7921 Serial Interface Timing Diagram
04350-0-007
12345 13141516
t
QUIET
t
ACQUISITION
1/THROUGHPUT
12.5(1/f
SCLK
)
t
CONVERT
BC
SCLK
CS
t
10
t
2
Figure 7. Serial Interface Timing Example
AD7911/AD7921
Rev. A | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 4.
Parameter Rating
V
DD
to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin except Supplies
1
±10 mA
Operating Temperature Range
Commercial (A Grade) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSOT Package
θ
JA
Thermal Impedance 207°C/W
MSOP Package
θ
JA
Thermal Impedance 205.9°C/W
θ
JC
Thermal Impedance 43.74°C/W
Lead Temperature Soldering
Reflow (10 s to 30 s) 235 (0/+5)°C
ESD 2 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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AD7921ARMZ

Mfr. #:
Buy AD7921ARMZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2CH 2.35-5.25V 250 kSPS 12-Bit
Lifecycle:
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