AD7921ARMZ Datasheet AD7921ARMZ-REEL7, AD7921ARMZ, AD7911AUJZ-R2 | P16-P18

AD7911/AD7921

Rev. A | Page 16 of 28

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the AD7911/

AD7921. V

REF

is taken internally from V

and as such V

should be well decoupled. This provides an analog input range

of 0 V to V

. The conversion result is output in a 16-bit word

with two leading zeros, followed by the channel identifier bit

that identifies the channel converted, followed by an invalid bit

that matches up to the channel converted, followed by the MSB

of the 12-bit or 10-bit result. For the AD7911, the 10-bit result is

followed by two trailing zeros. See the Serial Interface section.

Alternatively, because the supply current required by the

AD7911/AD7921 is so low, a precision reference can be used as

the supply source to the AD7911/AD7921. A REF19x voltage

reference (REF195 for 5 V or REF193 for 3 V) can be used to

supply the required voltage to the ADC (see Figure 22). This

configuration is especially useful, if the power supply is quite

noisy or if the system supply voltages are at some value other

than 5 V or 3 V (for example, 15 V). The REF19x outputs a

steady voltage to the AD7911/AD7921. If the low dropout

REF193 is used, the current it needs to supply to the AD7911/

AD7921 is typically 1.5 mA. When the ADC is converting at a

rate of 250 kSPS, the REF193 needs to supply a maximum of

2 mA to the AD7911/AD7921. The load regulation of the

REF193 is typically 10 ppm/mA (REF193, V

= 5 V), which

results in an error of 20 ppm (60 μV) for the 2 mA drawn from

it. This corresponds to a 0.082 LSB error for the AD7921 with

= 3 V from the REF193 and a 0.061 LSB error for the

AD7911.

For applications where power consumption is a concern, the

power-down mode of the ADC and the sleep mode of the

REF19x reference should be used to improve power perform-

ance. See the Modes of Operation section.

04350-0-021

AD7911/

AD7921

IN0

SERIAL

INTERFACE

V TO V

INPUT

IN1

GND

SCLK

DIN

DOUT

0.1

F10

TANT

0.1

680nF

SUPPLY

1.5mA

REF193

Figure 22. REF193 as Power Supply to AD7911/AD7921

Table 6 provides some typical performance data with various

references used as a V

source and a 50 kHz input tone under

the same setup conditions.

Table 6. AD7921 Performance for Various Voltage

References IC

Reference Tied to V

AD7921 SNR Performance (dB)

AD780 at 3 V −73

REF193 −72.42

ADR433 −72.9

AD780 at 2.5 V −72.86

REF192 −72.27

ADR421 −72.75

ANALOG INPUT

Figure 23 shows an equivalent circuit of the analog input

structure of the AD7911/AD7921. The two diodes, D1 and D2,

provide ESD protection for the analog input. Care must be

taken to ensure that the analog input signal never exceeds the

supply rails by more than 300 mV, because this would cause

these diodes to become forward biased and start conducting

current into the substrate. The maximum current these diodes

can conduct without causing irreversible damage to the part is

10 mA.

04350-0-022

6pF

20pF

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

Figure 23. Equivalent Analog Input Circuit

The capacitor C1 in Figure 23 is typically about 6 pF and can

primarily be attributed to pin capacitance. The resistor R1 is a

lumped component made up of the on resistance of a track-

and-hold switch and also includes the on resistance of the input

multiplexer. This resistor is typically about 100 Ω. The capacitor

C2 is the ADC sampling capacitor and has a capacitance of

20 pF typically.

For ac applications, removing high frequency components from

the analog input signal is recommended using a band-pass filter

on the relevant analog input pin. In applications where

harmonic distortion and signal-to-noise ratio are critical, the

analog input should be driven from a low impedance source.

Large source impedances can significantly affect the ac

performance of the ADC. This might necessitate the use of an

input buffer amplifier. The choice of the op amp is a function of

the particular application.

AD7911/AD7921

Rev. A | Page 17 of 28

DIN INPUT

Table 7 provides some typical performance data with various

op amps used as the input buffer, and a 50 kHz input tone

under the same setup conditions.

The channel to be converted on in the next conversion is

selected by writing to the DIN pin. Data on the DIN pin is

loaded into the AD7911/AD7921 on the falling edge of SCLK.

The data is transferred into the part on the DIN pin at the same

time that the conversion result is read from the part.

Table 7. AD7921 Performance for Various Input Buffers

Op Amp in the Input

Buffer

AD7921 SNR Performance (dB)

50 kHz Input , V

= 3.6 V

Single op amps

AD8038 −72.79

AD8510 −72.35

AD8021 −72.2

Dual op amps

AD712 −72.68

Only the third bit of the DIN word is used; the rest are ignored

by the ADC. The third MSB is the channel identifier bit, which

identifies the channel to be converted on in the next conversion,

IN0

(CHN = 0) or V

IN1

(CHN = 1).

04350-0-023

LSBMSB

X X CHN X DON'T CARE

AD8022 −72.88

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases and performance degrades (see

Figure 16).

Figure 24. AD7911/AD7921 DIN Word

DOUT OUTPUT

The conversion result from the AD7911/AD7921 is provided on

this output as a serial data stream. The bits are clocked out on

the SCLK falling edge at the same time that the conversion is

taking place.

DIGITAL INPUTS

The serial data stream for the AD7921 consists of two leading

zeros followed by the bit that identifies the channel converted,

an invalid bit that matches up to the channel identifier bit, and

the 12-bit conversion result with MSB provided first.

The digital inputs applied to the AD7911/AD7921 are not

limited by the maximum ratings that limit the analog input.

Instead, the digital inputs applied can go to 7 V and are not

restricted by the V

+ 0.3 V limit as on the analog input. For

example, if the AD7911/AD7921 are operated with a V

of 3 V,

then 5 V logic levels could be used on the digital inputs. How-

ever, it is important to note that the data output on DOUT still

has 3 V logic levels when V

= 3 V. Another advantage of

SCLK, DIN, and

not being restricted by the V

+ 0.3 V

limit is that power supply sequencing issues are avoided. If

DIN, or SCLK are applied before V

, then there is no risk of

latch-up as there would be on the analog inputs, if a signal

greater than 0.3 V were applied prior to V

For the AD7911, the serial data stream consists of two leading

zeros followed by the bit that identifies the channel converted,

an invalid bit that matches up to the channel identifier bit, and

the 10-bit conversion result with MSB provided first, followed

by two trailing zeros.

04350-0-024

LSB

AD7911

MSB

00 0 0CHN X CONVERSION RESULT

AD7921

0 0 CHN X CONVERSION RESULT

Figure 25. AD7911/AD7921 DOUT Word

AD7911/AD7921

Rev. A | Page 18 of 28

MODES OF OPERATION

The two modes of operation of the AD7911/AD7921 are

normal mode and power-down mode. The mode of operation is

selected by controlling the logic state of the

signal. The point

at which

is pulled high after the conversion has been initi-

ated determines whether the AD7911/AD7921 enter power-

down mode. Similarly, if already in power-down mode,

can

control whether the device returns to normal operation or

remains in power-down mode.

Power-down mode is designed to provide flexible power

management options and to optimize the ratio of power

dissipation to throughput rate for different application

requirements.

NORMAL MODE

Normal mode is intended for the fastest throughput rate

performance. The user does not have to worry about any

power-up time, because the AD7911/AD7921 remain fully

powered all the time. Figure 26 shows the operation of the

AD7911/AD7921 in this mode.

The conversion is initiated on the falling edge of

, as

described in the section. To ensure that the part

remains fully powered up at all times,

Serial Interface

must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

. If

is brought high any time after the 10th SCLK falling

edge but before the end of t

CONVERT

, the part remains powered-

up, but the conversion is terminated and DOUT goes back into

three-state. For the AD7911/AD7921, a minimum of 14 and

16 serial clock cycles, respectively, are needed to complete the

conversion and access the complete conversion result.

can idle high until the next conversion or can idle low until

returns high sometime prior to the next conversion

(effectively idling

low). Once a data transfer is complete

(DOUT has returned to three-state), another conversion can be

initiated after the quiet time, t

QUIET

, has elapsed by bringing

low again.

POWER-DOWN MODE

Power-down mode is intended for use in applications where

slower throughput rates are required. Either the ADC is

powered down between each conversion, or a series of

conversions can be performed at a high throughput rate and

then the ADC is powered down for a relatively long duration

between these bursts of several conversions. When the

AD7911/AD7921 are in power-down mode, all analog circuitry

is powered down.

To enter power-down mode, the conversion process must be

interrupted by bringing

high any time after the second

falling edge of SCLK and before the 10th falling edge of SCLK,

as shown in . Once Figure 27

has been brought high in this

window of SCLKs, then the part enters power-down mode, the

conversion that was initiated by the falling edge of

terminated, and DOUT goes back into three-state. If

brought high before the second SCLK falling edge, then the part

remains in normal mode and does not power down. This helps

to avoid accidental power-down due to glitches on the

line.

To exit this mode of operation and power the AD7911/AD7921

up again, a dummy conversion is performed. On the falling

edge of

, the device begins to power up and continues to

power up as long as

is held low until after the falling edge of

the 10th SCLK. The device is fully powered up once 16 SCLKs

have elapsed and valid data results from the next conversion, as

shown in . If Figure 28

is brought high before the 10th falling

edge of SCLK, then the AD7911/AD7921 go back into power-

down mode. This helps to avoid accidental power-up due to

glitches on the

line or an inadvertent burst of 8 SCLK cycles

while

is low. Therefore, although the device might begin to

power up on the falling edge of

, it powers down again on the

rising edge of

, as long as this occurs before the 10th SCLK

falling edge.

04350-0-025

1 10 12 14 16 1 10 12 14 16

AD7911/AD7921

SCLK

DIN

DOUT

CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION

CONVERSION RESULT CONVERSION RESULT

Figure 26. Normal Mode Operation

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AD7921ARMZ

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Description:

Analog to Digital Converters - ADC 2CH 2.35-5.25V 250 kSPS 12-Bit

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