AFBR-5978Z
Digital Diagnostic 650nm Transceiver for Fast Ethernet
(10/100 Mbps) with SC-RJ connector
Data Sheet
Features
Compatible with electrical and optical performance
of the POFAC recommendations for the Fast Ethernet
over Plastic Optical Fiber (POF).
Compatible with the Electrical and Optical perfor-
mance of the ProNet recommendations the Fast
Ethernet over POF and Hard-Clad Silica Fiber (HCS).
Manufactured in an ISO 9001 certied facility
DMI [Digital Diagnostics Monitoring Interface,
SFF-8472 Rev 9.3], provides real-time monitoring of:
- Temperature
- Supply voltage
- Received Optical Power (Alarm/Warning ag)
LVPECL Signal Detect Output
Temperature range –25 to +85 °C
Applications
Factory automation at Fast Ethernet speeds
Fast Ethernet networking over POF and HCS
Link Distance up to 50 m POF or 100 m HCS
(See application note 5290 for details)
HCS® is a trademark of OFS Corporation
AFBR-5978Z is compatible with the SC-RJ Connecting System from
Reichle & De-Massari AG, Switzerland
Description
The AFBR-5978Z transceiver provides the system de-
signer with the ability to implement Fast Ethernet (100
Mbps) or Ethernet (10 Mbps) over 50 meter standard
bandwidth 0.5±0.05 NA POF and 100 meter standard
bandwidth 0.37±0.04 NA HCS ber. The connectivity
available for the transceiver is SC-RJ. This product is lead
free and compliant with RoHS.
Transmitter
The transmitter contains a 650nm LED with an integrat-
ed driver. The LED driver operates at 3.3 V. It receives a
LVPECL compatible electrical input, and converts it into
a modulated current driving the LED. The LED is pack-
aged in an optical subassembly, part of the transmitter
section. The optical subassembly couples the output
optical power eciently into POF or HCS ber.
Receiver
The receiver utilizes a Si PIN photodiode. The PIN pho-
todiode is packaged in an optical sub-assembly, part of
the receiver section. This optical subassembly couples
the optical power eciently from POF or HCS ber to
the receiving PIN. The integrated IC operates at 3.3 V and
converts the photocurrent into LVPECL compatible elec-
trical output.
Package
The transceiver package consist of four basic elements;
two optical subassemblies, an electrical subassembly
and the housing as illustrated in the block diagrams in
Figure 1. The package outline drawing and pin out are
shown in Figures 2 and 3.
Patent - www.avagotech.com/patents
2
Block diagram
Figure 1. Block diagram
DATA OUT
SIGNAL
DETECT OUT
DATA IN
ELECTRICAL SUBASSEMBLY
QUANTIZER IC
DRIVER IC
TOP VIEW
PIN PHOTODIODE
SC-RJ
RECEPTACLE
OPTICAL
SUBASSEMBLIES
LED
PREAMP IC
DIFFERENTIAL
SINGLE-ENDED
DIFFERENTIAL
DMI
Figure 2. Package outline drawing.
The optical subassemblies utilize a high volume assem-
bly process together with low cost lens elements which
result in a cost eective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the IC chips
and various surface mounted passive circuit elements
are attached.
The housing includes internal shields for the electri-
cal and optical subassemblies to insure low EMI emis-
sions and high immunity to external EMI elds. The
outer housing including the duplex SC-RJ connector is
molded of lled non-conductive plastic to provide me-
chanical strength and electrical isolation. The low prole
of the Avago Technologies transceiver design complies
with the maximum height allowed for the duplex SC-RJ
connector over the entire length of the package.
The transceiver is attached to a printed circuit board
with twelve signal pins and the two solder posts, which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand
the mechanical loads imposed on the transceiver by
mating with the SC-RJ connectored ber cables. The
solder posts are isolated from the circuit design of the
transceiver and do not require connection to a ground
plane on the circuit board
3
Pin Descriptions
Pin 1 Sda: the data line of the two wire serial interface.
This data line should be pulled up with a 4.7k–10k re-
sistor on the host board to a supply of 3.3V ±10%.
Pin 2 Rx GND: receiver ground pin. Directly connect this
pin to the receiver ground plane of the host board.
Pin 3 Rx Vcc: receiver power supply pin. Provide +3.3 V
DC via a receiver power supply lter circuit. Locate the
power supply lter circuit as close as possible to the Vcc
Rx pin.
Pin 4 Sd: signal detect pin. If an optical signal is present
at the input of the receiver, Sd output is a logic “1”.
Absence of an optical signal to the receiver results in a
logic “0” output. This signal detect output can be used
to drive a LVPECL input on an upstream circuit, such as
Signal Detect input or Loss of Signal–bar. Proper LVPECL
termination should be in place. See gure 4.
Pin 5 Rdata-: receiver data out bar. This data line is a 3.3V
LVPECL compatible dierential line which should be
properly terminated with a 130 pull up to Vcc and 82
pull down to ground.
Pin 6 Rdata+: receiver data out. This data line is a 3.3V
LVPECL compatible dierential line which should be
properly terminated with a 130 pull up to Vcc and 82
pull down to ground.
Figure 3. Pin Out diagram
Pin 7 Tx Vcc: transmitter power supply. Provide +3.3V DC
via a transmitter power supply lter circuit. Locate the
power supply lter circuit as close as possible to the Vcc
Tx pin.
Pin 8 Tx GND: transmitter ground. Directly connect this
pin to the transmitter ground plane on the host board.
Pin 9 Txdis: transmitter disable input. This input is used
to shut down the transmitter light output. It is internally
pulled up with a ~8 k resistor.
Low (0-0.8 V) - transmitter on
Between (0.8-2.0 V) - undened
High (2.0-3.63 V) – transmitter o
Open – transmitter o
Pin 10 Tdata+: transmitter data in. This data line is an AC
coupled 100 dierential line which does not need any
termination at the user SERDES. The AC coupling is done
inside the module and therefore not required on the
host board.
Pin 11 Tdata-: transmitter data in bar. This data line is an
AC coupled 100 dierential line which does not need
any termination at the user SERDES. The AC coupling is
done inside the module and therefore not required on
the host board.
Pin 12 Scl: the clock line of the two wire serial interface.
This data line should be pulled up with a 4.7k – 10 k
resistor on the host board to a supply of 3.3V ±10%.
Sda
RxGND
RxVcc
Sd
Rdata-
Rdata+
Scl
Tdata-
Tdata+
Txdis
TxGND
TxVcc
bottom view
SC-RJ connector

AFBR-0978Z

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Development Tools 650nm FE Transceiver Eval Kit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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