AFBR-0978Z Datasheet AFBR-0978Z, AFBR-5978Z | P4-P6

Figure 4. Recommended termination circuit.

PC Master

AFBR-5978Z

Protocol IC & SERDES

LED driver

Amplifier &

Tx disable

TD+

TD-

RD+

RD-

Signal Detect

Txdis

Tdata+

TxVcc

Tdata-

Rdata+

Rdata-

Sda

Scl

EEPROM

100

10nF

130 130

82 82

4.7k-10k 4.7k-10k

V cc 3.3V

130

1µH

10µF 0.1µF

0.1µF

V cc 3.3V

10µF 0.1µF

V cc 3.3V

Z = 50 Ω

RxVcc

Quantisizer

Board Layout – Decoupling Circuit and Ground Planes

It is important to take care in the layout of your circuit

board to achieve optimum performance from the trans-

ceiver. A power supply decoupling circuit is recom-

mended to lter out noise to assure optimal product

performance. It is further recommended that a contigu-

ous ground plane be provided in the circuit board di-

rectly under the transceiver to provide a low inductance

ground for signal return current. This recommendation

is in keeping with good high frequency board layout

practices.

Functional Data I/O

The LVPECL receiver output of the Avago Technologies

transceiver can be DC-coupled to the LVPECL compli-

ant network interface through a Thèvenin equivalent

transformation. For a 3.3V power supply the LVPECL

outputs should be pulled up to Vcc with a 130Ω resistor

and pulled down to ground with an 82Ω resistor. Both

coupling resistors are preferably placed close to the

network interface IC, see gure 4. AC-coupling can be

used for systems in which the transceiver and connected

logic are at dierent supply voltages. For AC coupling,

the coupling capacitor should be large enough to avoid

excessive low-frequency droop when the data signal

contains long strings of consecutive identical digits. The

LVPECL outputs have to be pulled down to ground rst

to DC bias the output before AC coupling. Because the

LVPECL output common-mode voltage is xed at Vcc

– 1.3V, the DC-biasing resistor can be selected by as-

suming 14 mA DC current. This results in a bias-resistor

value of 142Ω - 200Ω. After the AC-coupling capacitors,

a Thèvenin equivalent transformation connects to the

LVPECL compatible network interface, equal to the one

used in DC-coupling.

Figure 5. Digital diagnostic memory map – specic data eld description

(from SFF-8472 MSA)

The diagnostic monitoring interface (DMI) has two 256

byte memory maps in EEPROM which are accessible

over a two wire interface: the serial ID memory map

at address 1010000X (0xA0) and the digital diagnostic

memory map at address 1010001X (0xA2).

The serial ID memory map contains a serial identica-

tion and vendor specic information and is read only.

The digital diagnostic memory map contains device

operating parameters and alarm and warning ags. The

operating parameters are to be retrieved through a se-

quential read command ensuring that the MSB and LSB

of each parameter are “coherent”. Furthermore, it con-

tains 120 bytes that can be written by the user as well as

a writable soft control byte.

Tables 1 to 6 detail memory contents, timing character-

istics, soft commands and alarm/warning ags.

Digital Diagnostics Monitoring Interface

The AFBR-5978Z transceiver features an enhanced

digital diagnostic interface, compliant to the “Digital Di-

agnostic Monitoring Interface for Optical Transceivers”

SFF-8472 Multi-source Agreement (MSA). Please refer to

the MSA document to access information on the range

of options, both hardware and software, available to the

host system for exploiting the available digital diagnos-

tic features.

The enhanced digital interface allows real-time access

to device operating parameters, and includes optional

digital features such as soft control and monitoring of

I/O signals. In addition, it fully incorporates the func-

tionality needed to implement digital alarms and warn-

ings, as dened by the SFF-8472 MSA. With the digital

diagnostic monitoring interface, the user has capability

of performing component monitoring, fault isolation

and failure prediction in their transceiver-based applica-

tions.

2 wire address 1010000X (A0h) 2 wire address 1010001X (A2h)

127

255

Serial ID Dened by

SFP MSA (96 bytes)

Vendor Specic

(32 bytes)

Reserved in SFP

MSA (128 bytes)

Alarm and Warning

Thresholds (56 bytes)

Cal Constants

(40 bytes)

119

Time Diagnostic

Interface (24 bytes)

247

User Writable

EEPROM (120 bytes)

Vendor Specic (8 bytes)

255

127

Vendor Specic (8 bytes)

Table 1. Transceiver soft diagnostics Timing characteristics

Parameter Symbol Min Max Unit Notes

Hardware TX_DISABLE assert time t_o 10 µs Note 1, Figure 6

Hardware TX_DISABLE negate time t_on 1 ms Note 2, Figure 6

Time to initialize t_init 100 ms Note 3, Figure 6

Hardware RX_SD assert time t_sd_on 100 µs Note 4

Hardware RX_SD de-assert time t_sd_o 100 µs Note 5

Software TX_DISABLE assert time t_o_soft 100 ms Note 6

Software TX_DISABLE negate time t_on_soft 100 ms Note 7

Software RX_SD assert time t_sd_on_soft 100 ms Note 8

Software RX_SD de-assert time t_sd_o_soft 100 ms Note 9

Analog parameter data ready t_data 1000 ms Note 10

Serial bus hardware ready t_serial 300 ms Note 11

Write cycle time t_write 10 ms Note 12

Serial ID clock rate f_serial_clock 400 kHz Note 13

Notes:

1. Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal.

2. Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal.

3. Time from Power on or falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal.

4. Time from valid optical signal to RX_SD assertion.

5. Time from loss of optical signal to RX_SD de-assertion.

6. Time from two-wire interface assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. Measured

from falling clock edge after stop bit of write transaction.

7. Time from two-wire interface de-assertion of TX_DISABLE (A2h, byte110, bit 6) to when the modulated optical output rises above 90% of

nominal.

8. Time for two-wire interface assertion of RX_SD (A2h, byte 110, bit 1) from presence of valid optical signal.

9. Time for two-wire interface de-assertion of RX_SD (A2h, byte 110, bit 1) from loss of optical signal.

10. From power on to data ready bit asserted (A2h, byte 110, bit 0). Data ready indicates analog monitoring circuitry is operational.

11. Time from power on until module is ready for data transmission over the serial bus (reads or writes over A0h and A2h).

12. Time from stop bit to completion of a 1-8 byte write command.

13. Contact Avago Technologies for applications at faster (>400 kHz) Serial ID clock rates.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

AFBR-0978Z

Mfr. #:

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Manufacturer:

Broadcom / Avago

Description:

Fiber Optic Development Tools 650nm FE Transceiver Eval Kit

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AFBR-0978Z

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