AD9572ACPZPEC Datasheet AD9572ACPZLVD, AD9572ACPZPEC, AD9572ACPZLVD-R7 | P1-P3

Fiber Channel/Ethernet Clock Generator IC,

7 Clock Outputs

AD9572

Rev. B

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FEATURES

Fully integrated dual VCO/PLL cores

0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz

0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz

Input crystal or clock frequency of 25 MHz

Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,

100 MHz, and 125 MHz

Choice of LVPECL or LVDS output format

Integrated loop filters

Copy of reference clock output

Rates configured via strapping pins

0.71 W power dissipation (LVDS operation)

1.07 W power dissipation (LVPECL operation)

3.3 V operation

Space saving, 6 mm × 6 mm, 40-lead LFCSP

APPLICATIONS

Fiber channel line cards, switches, and routers

Gigabit Ethernet/PCIe support included

Low jitter, low phase noise clock generation

FUNCTIONAL BLOCK DIAGRAM

XTAL

OSC

REFCLK

REFSEL

1 × 25MHz

CMOS

FREQSEL

AD9572

2 × 106.25MHz

VCO

PFD/CP

LPF THIRD

ORDER

DIVIDERS

LVPECL

OR LVDS

2 × 100MHz

OR 125MHz

VCO

PFD/CP

LPF

3RD ORDER

DIVIDERS

LVPECL

OR LVDS

1 × 156.25MHz

LVPECL

OR LVDS

FORCE_LOW

1 × 33.33MHz

CMOS

LDO

7498-001

Figure 1.

GENERAL DESCRIPTION

The AD9572 provides a multioutput clock generator function

along with two on-chip PLL cores, optimized for fiber channel

line card applications that include an Ethernet interface. The

integer-N PLL design is based on the Analog Devices, Inc.,

proven portfolio of high performance, low jitter frequency

synthesizers to maximize network performance. Other applica-

tions with demanding phase noise and jitter requirements also

benefit from this part.

The PLL section consists of a low noise phase frequency

detector (PFD), a precision charge pump (CP), a low phase

noise voltage controlled oscillator (VCO), and a preprogrammed

feedback divider and output divider. By connecting an external

crystal or reference clock to the REFCLK pin, frequencies up to

156.25 MHz can be locked to the input reference. Each output

divider and feedback divider ratio is preprogrammed for the

required output rates.

A second PLL also operates as an integer-N synthesizer and

drives two LVPECL or LVDS output buffers for 106.25 MHz

operation. No external loop filter components are required, thus

conserving valuable design time and board space.

The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame

chip scale package (LFCSP) and can be operated from a single

3.3 V supply. The temperature range is −40°C to +85°C.

QUAD SFP

PHY

QUAD SFP

PHY

QUAD SFP

PHY

QUAD SFP

PHY

16-PORT FIBRE CHANNEL ASIC

10G SFP+

CPU

ISLAND

AD9572

1 × 156.25MHz

2 × 106.25MHz

1 × 100MHz/125MHz

1 × 25MHz

1 × 33.33MHz

7498-002

Figure 2. Typical Application

AD9572* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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EVALUATION KITS

• AD9572 Evaluation Board

DOCUMENTATION

Data Sheet

• AD9572: Fiber Channel/Ethernet Clock Generator IC, PLL

Core, Dividers, 7 Clock Outputs Data Sheet

TOOLS AND SIMULATIONS

• AD9571/AD9572 IBIS Model

DESIGN RESOURCES

• AD9572 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

DISCUSSIONS

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SAMPLE AND BUY

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AD9572

Rev. B | Page 2 of 20

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

PLL Characteristics ...................................................................... 3

LVDS Clock Output Jitter............................................................ 4

LVPECL Clock Output Jitter....................................................... 5

CMOS Clock Output Jitter.......................................................... 5

Reference Input............................................................................. 5

Clock Outputs ............................................................................... 6

Timing Characteristics ................................................................ 6

Control Pins .................................................................................. 7

Power.............................................................................................. 7

Crystal Oscillator.......................................................................... 7

Timing Diagrams.............................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution...................................................................................9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

Outputs ........................................................................................ 16

Phase Frequency Detector (PFD) and Charge Pump............ 17

Power Supply............................................................................... 17

CMOS Clock Distribution ........................................................ 17

LVPECL Clock Distribution..................................................... 18

LVDS Clock Distribution.......................................................... 18

Reference Input........................................................................... 18

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 19



Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

/11—Rev. A to Rev. B

hanges to Output Rise Time, t

RC2

Parameter and Output Fall

Time, t

FC2

Parameter in Table 7....................................................... 6

11/10—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Table 2............................................................................ 4

Changes to Table 3 and Table 4....................................................... 5

Changes to Table 7............................................................................ 6

Added Figure 7 and Figure 8......................................................... 11

Added Figure 14, Figure 15, and Figure 16 ................................. 13

Deleted Original Figure 16 and Figure 19................................... 16

Renumbered Figures Sequentially............................... Throughout

Changes to CMOS Clock Distribution Section.......................... 17

Changes to LVPECL Clock Distribution Section, Added

Figure 23 and Figure 24 ................................................................. 18

Changes to LVDS Clock Distribution Section, Added

Figure 26 .......................................................................................... 18

Changes to Reference Input Section ............................................ 18

Changes to Power and Grounding Considerations and Power

Supply Rejection Section............................................................... 19

7/09—Revision 0: Initial Version

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD9572ACPZPEC

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Manufacturer:

Analog Devices Inc.

Description:

Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output

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AD9572ACPZPEC

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