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AD9572ACPZPEC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD9572
Rev. B | Page 9 of 20
ABSOLUTE MAXIMUM RATINGS
Table 11.
Parameter Rating
VS to GND −0.3 V to +3.6 V
REFCLK to GND −0.3 V to VS + 0.3 V
BYPASSx to GND −0.3 V to VS + 0.3 V
XO to GND −0.3 V to VS + 0.3 V
FREQSEL, FORCE_LOW, and
REFSEL to GND
−0.3 V to VS + 0.3 V
25M, 33M, 100M/125M, 106M, and
156M to GND
−0.3 V to VS + 0.3 V
Junction Temperature
1
150°C
Storage Temperature Range −65°C to +150°C
1
See Table 12 for θ
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Thermal impedance measurements were taken on a 4-layer
board in still air in accordance with EIA/JESD51-7.
Table 12. Thermal Resistance
Package Type θ
JA
Unit
40-Lead LFCSP 27.5 °C/W
ESD CAUTION
AD9572
Rev. B | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. * = SHORT TO PIN 36.
2
. ** = SHORT TO PIN 14.
3. NC = NO CONNECT.
4
. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICA
L
CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO
FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND).
PIN 1
INDICATOR
1GND
2VS
3NC
425M
5VS
6XO
7XO
8REFCLK
9REFSEL
10GND
23 33M
24 VS
25 VS
26 VS
27 FREQSEL
28 VS
29 106M
30 106M
22 100M/125M
21 100M/125M
11
VS
12
**
13
**
15
VS
17
156M
16
VS
18
156M
19
100M/125M
20
100M
/125M
14
BYPASS2
33
VS
34
GND
35
VS
36
BYPASS1
37
FORCE_LO
W
38
*
39
VS
40
VS
32
106M
31
106M
TOP VIEW
(Not to Scale)
AD9572
07498-007
Figure 6. Pin Configuration
Table 13. Pin Function Descriptions
1
Pin No. Mnemonic Description
1, 10, 34 GND Ground. Includes external paddle (EPAD).
2 VS Power Supply Connection for the 25M CMOS Buffer.
3 NC
No Connect. This pin should be left floating.
4 25M
CMOS 25 MHz Output.
5 VS
Power Supply Connection for the Crystal Oscillator.
6, 7 XO
External 25 MHz Crystal.
8 REFCLK
25 MHz Reference Clock Input. Tie low when not in use.
9 REFSEL
Logic Input. Used to select the reference source.
11 VS
Power Supply Connection for the GbE PLL.
12, 13 N/A
Short to Pin 14.
14, 36 BYPASS2, BYPASS1
These pins are for bypassing each LDO to ground with a 220 nF capacitor.
15 VS
Power Supply Connection for the GbE VCO.
16 VS
Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers.
17 156M
LVPECL/LVDS Output at 156.25 MHz.
18
156M
Complementary LVPECL/LVDS Output at 156.25 MHz.
19, 21 100M/125M
LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping.
20, 22
100M
/125M
Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz.
23 33M
CMOS 33.33 MHz Output.
24 VS
Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers.
25 VS
Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers.
26 VS
Power Supply Connection for the GbE PLL Feedback Divider.
27 FREQSEL
Logic Input. Used to configure output drivers.
28 VS
Power Supply Connection for the FC PLL Feedback Divider.
29, 31
106M
LVPECL/LVDS Output at 106.25 MHz.
30, 32 106M Complementary LVPECL/LVDS Output at 106.25 MHz.
AD9572
Rev. B | Page 11 of 20
Pin No. Mnemonic Description
33 VS Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers.
35 VS Power Supply Connection for the FC VCO.
37 FORCE_LOW
Forces the 33.33 MHz output into a low state.
38 N/A
Short to Pin 36.
39 VS
Power Supply Connection for the FC PLL.
40 VS Power Supply Connection for Miscellaneous Logic.
1
The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to
ground (GND).
07498-024
50Ω
50Ω
C
D
V
S
C
D
V
S
C
D
V
S
C
D
V
S
R
T
= 100Ω
0.22µF
C
D
= 100nF||10nF
C
D
V
S
C
D
V
S
V
S
C
D
R
T
= 100Ω
50Ω
50Ω
R
T
= 100Ω
50Ω
50Ω
C
D
V
S
C
D
V
S
25MHz
C
X
= 22pF
C
X
= 22pF
50Ω
T
O CMOS
INPUT
C
D
V
S
C
D
V
S
C
D
V
S
C
D
V
S
R
T
= 100Ω
50Ω
50Ω
R
T
= 100Ω
50Ω
50Ω
50Ω
TO CMOS
INPUT
AD9572
106M
100M/125M
VS
VS
VS
VS
33M
FREQSEL
106M
106M
VS
VS
VS
VS
GND
GND
NC
VS
25M
VS
XO
XO
REFCLK
REFSEL
GND
BYPASS1
TEST
FORCE_LOW
VS
TEST
TEST
VS
VS
156M
100M/125M
BYPASS2
106M
100M/125M
100M/125M
156M
0.22µF
Figure 7. Typical Application Schematic, LVDS Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz
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AD9572ACPZPEC

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Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output
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