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AD9572ACPZPEC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD9572
Rev. B | Page 12 of 20
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
07498-025
C
D
V
S
C
D
V
S
0.22µF
V
S
V
S
V
S
C
D
50Ω
50Ω
C
D
V
S
C
D
V
S
25MHz
C
X
= 22pF
C
X
= 22pF
50Ω
T
O CMOS
INPUT
C
D
= 100nF||10nF
C
D
C
D
V
S
V
S
C
D
V
S
C
D
V
S
C
D
0.22µF
V
S
C
D
V
S
C
D
V
S
C
D
V
S
TO CMOS
INPUT
AD9572
106M
100M/125M
VS
VS
VS
VS
33M
FREQSEL
106M
106M
VS
VS
VS
VS
GND
GND
NC
VS
25M
VS
XO
XO
REFCLK
REFSEL
GND
BYPASS1
TEST
FORCE_LOW
VS
TEST
TEST
VS
VS
156M
100M/125M
BYPASS2
106M
100M/125M
100M/125M
156M
VS VS
127Ω 127Ω
83Ω 83Ω
V
S
V
S
127Ω 127Ω
83Ω 83Ω
VS VS
127Ω 127Ω
127Ω
127Ω
83Ω
83Ω
83Ω
83Ω
VS VS
127Ω 127Ω
83Ω 83Ω
Figure 8. Typical Application Schematic, LPECL Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz
AD9572
Rev. B | Page 13 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Phase noise plots taken with 100 MHz and 125 MHz outputs enabled; 33.3 MHz output disabled.
07498-008
100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07498-011
100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
Figure 9. 106.25 MHz Phase Noise
Figure 12. 156.25 MHz Phase Noise
07498-009
100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07498-012
100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
Figure 10. 125 MHz Phase Noise
Figure 13. 100 MHz Phase Noise
07498-010
100
–160
–150
–140
–130
–120
–110
1k 10k 100k 1M 100M10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
10ns/DIV
500mV/DI
V
07498-026
Figure 14. 25 MHz CMOS Output, 3.9 pF Load Capacitance on Evaluation
Board, Active-Probe Measurement, R
probe
=20 kΩ, C
probe
=1 pF
Figure 11. 25 MHz Phase Noise
AD9572
Rev. B | Page 14 of 20
2ns/DIV
200mV/DI
V
07498-027
Figure 15. 156.25 MHz LVPECL Output, Differential Plot, 200 Ω Termination
to GND on Evaluation Board, AC-Coupled via 0.1 μF Capacitors to
Oscilloscope Set to 50 Ω Input Termination
2ns/DIV
100mV/DI
V
07498-028
Figure 16. 125 MHz LVDS Output, Differential Plot, AC-Coupled via 0.1 μF
Capacitors to Oscilloscope Set to 50 Ω Input Termination
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD9572ACPZPEC

Mfr. #:
Buy AD9572ACPZPEC
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output
Lifecycle:
New from this manufacturer.
Delivery:
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