OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD9572ACPZPEC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD9572
Rev. B | Page 3 of 20
SPECIFICATIONS
PLL CHARACTERISTICS
Typical (typ) is given for V
S
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE NOISE CHARACTERISTICS
PLL Noise (106.25 MHz LVDS Output)
At 1 kHz −123 dBc/Hz 33.33 MHz output disabled
At 10 kHz −127 dBc/Hz 33.33 MHz output disabled
At 100 kHz −129 dBc/Hz 33.33 MHz output disabled
At 1 MHz −150 dBc/Hz 33.33 MHz output disabled
At 10 MHz −152 dBc/Hz 33.33 MHz output disabled
At 30 MHz −153 dBc/Hz 33.33 MHz output disabled
PLL Noise (156.25 MHz LVDS Output)
At 1 kHz −118 dBc/Hz 33.33 MHz output disabled
At 10 kHz −125 dBc/Hz 33.33 MHz output disabled
At 100 kHz −126 dBc/Hz 33.33 MHz output disabled
At 1 MHz −145 dBc/Hz 33.33 MHz output disabled
At 10 MHz −151 dBc/Hz 33.33 MHz output disabled
At 30 MHz −151 dBc/Hz 33.33 MHz output disabled
PLL Noise (125 MHz LVDS Output)
At 1 kHz −119 dBc/Hz 33.33 MHz output disabled
At 10 kHz −127 dBc/Hz 33.33 MHz output disabled
At 100 kHz −128 dBc/Hz 33.33 MHz output disabled
At 1 MHz −147 dBc/Hz 33.33 MHz output disabled
At 10 MHz −151 dBc/Hz 33.33 MHz output disabled
At 30 MHz −152 dBc/Hz 33.33 MHz output disabled
PLL Noise (100 MHz LVDS Output)
At 1 kHz −121 dBc/Hz 33.33 MHz output disabled
At 10 kHz −128 dBc/Hz 33.33 MHz output disabled
At 100 kHz −130 dBc/Hz 33.33 MHz output disabled
At 1 MHz −147 dBc/Hz 33.33 MHz output disabled
At 10 MHz −150 dBc/Hz 33.33 MHz output disabled
At 30 MHz −150 dBc/Hz 33.33 MHz output disabled
PLL Noise (106.25 MHz LVPECL Output)
At 1 kHz −121 dBc/Hz 33.33 MHz output disabled
At 10 kHz −128 dBc/Hz 33.33 MHz output disabled
At 100 kHz −129 dBc/Hz 33.33 MHz output disabled
At 1 MHz −151 dBc/Hz 33.33 MHz output disabled
At 10 MHz −154 dBc/Hz 33.33 MHz output disabled
At 30 MHz −155 dBc/Hz 33.33 MHz output disabled
PLL Noise (156.25 MHz LVPECL Output)
At 1 kHz −119 dBc/Hz 33.33 MHz output disabled
At 10 kHz −125 dBc/Hz 33.33 MHz output disabled
At 100 kHz −126 dBc/Hz 33.33 MHz output disabled
At 1 MHz −147 dBc/Hz 33.33 MHz output disabled
At 10 MHz −152 dBc/Hz 33.33 MHz output disabled
At 30 MHz −153 dBc/Hz 33.33 MHz output disabled
AD9572
Rev. B | Page 4 of 20
Parameter Min Typ Max Unit Test Conditions/Comments
PLL Noise (125 MHz LVPECL Output)
At 1 kHz −122 dBc/Hz 33.33 MHz output disabled
At 10 kHz −127 dBc/Hz 33.33 MHz output disabled
At 100 kHz −128 dBc/Hz 33.33 MHz output disabled
At 1 MHz −148 dBc/Hz 33.33 MHz output disabled
At 10 MHz −152 dBc/Hz 33.33 MHz output disabled
At 30 MHz −153 dBc/Hz 33.33 MHz output disabled
PLL Noise (100 MHz LVPECL Output)
At 1 kHz −122 dBc/Hz 33.33 MHz output disabled
At 10 kHz −128 dBc/Hz 33.33 MHz output disabled
At 100 kHz −130 dBc/Hz 33.33 MHz output disabled
At 1 MHz −148 dBc/Hz 33.33 MHz output disabled
At 10 MHz −150 dBc/Hz 33.33 MHz output disabled
At 30 MHz −151 dBc/Hz 33.33 MHz output disabled
PLL Noise (33.33 MHz CMOS Output)
At 1 kHz −130 dBc/Hz
At 10 kHz −138 dBc/Hz
At 100 kHz −139 dBc/Hz
At 1 MHz −152 dBc/Hz
At 5 MHz −152 dBc/Hz
Phase Noise (25 MHz CMOS Output)
At 1 kHz −133 dBc/Hz
At 10 kHz −142 dBc/Hz
At 100 kHz −148 dBc/Hz
At 1 MHz −148 dBc/Hz
At 5 MHz −148 dBc/Hz
Spurious Content
1
−70 dBc Dominant amplitude, all outputs active
PLL Figure of Merit −217.5 dBc/Hz
1
When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content might be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for V
S
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 2.
Jitter Integration
Bandwidth (Typ) 100 MHz 106.25 MHz
125 MHz 33M
= Off/On
1
156.25 MHz Unit Test Conditions/Comments
12 kHz to 20 MHz 0.51 0.44 0.42/0.88 0.42
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
1.875 MHz to
20 MHz
0.19
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
637 kHz to 10 MHz 0.22
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
200 kHz to 10 MHz 0.32 0.25/0.78
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
12 kHz to 35 MHz 0.50 (off only)
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×
106.25 MHz
1
The typical 125 MHz rms jitter data is collected from the differential pair, Pin 21 and Pin 22, unless otherwise noted.
AD9572
Rev. B | Page 5 of 20
LVPECL CLOCK OUTPUT JITTER
Typical (typ) is given for V
S
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 3.
Jitter Integration
Bandwidth (Typ)
100
MHz
106.25
MHz
125 MHz
33M =
Off/On
156.25
MHz Unit Test Conditions/Comments
12 kHz to 20 MHz (Typ) 0.61 0.45 0.44/2.2 0.46 ps rms
LVPECL output frequency combinations are 1 × 156.25
MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz
12 kHz to 20 MHz (Max) 0.87 0.81
0.56 (off
only)
0.56 ps rms
LVPECL output frequency combinations are 1 × 156.25
MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz
1.875 MHz to 20 MHz (Typ) 0.28 ps rms
LVPECL output frequency combinations are 1 × 156.25
MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz
637 kHz to 10 MHz (Typ) 0.23 ps rms
LVPECL output frequency combinations are 1 × 156.25
MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz
200 kHz to 10 MHz (Typ) 0.38 0.24/2.2 ps rms
LVPECL output frequency combinations are 1 × 156.25
MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz
12 kHz to 35 MHz (Typ)
0.52 (off
only)
ps rms
LVPECL output frequency combinations are 156.25
MHz unterminated, 2 × 125 MHz, 2 × 106.25 MHz
12 kHz to 35 MHz (Max)
0.66 (off
only)
ps rms
LVPECL output frequency combinations are 156.25
MHz unterminated, 2 × 125 MHz, 2 × 106.25 MHz
CMOS CLOCK OUTPUT JITTER
Typical (typ) is given for V
S
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 4.
Jitter Integration Bandwidth 25 MHz 33.3 MHz Unit Test Conditions/Comments
12 kHz to 5 MHz (Typ) 0.78 0.41 ps rms
12 kHz to 5 MHz (Max) 1.1 N/A ps rms
200 kHz to 5 MHz (Typ) 0.76 0.52 ps rms
200 kHz to 5 MHz (Max) 1.0 N/A ps rms
REFERENCE INPUT
Typical (typ) is given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full V
S
and T
A
(−40°C to +85°C) variation.
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK INPUT (REFCLK)
Input Frequency 25 MHz
Input High Voltage 2.0 V
Input Low Voltage 0.8 V
Input Current −1.0 +1.0 μA
Input Capacitance 2 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD9572ACPZPEC

Mfr. #:
Buy AD9572ACPZPEC
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet