11AA02E48/11AA02E64
DS20002122D-page 4 2008-2016 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING – START HEADER
FIGURE 1-2: BUS TIMING – DATA
FIGURE 1-3: BUS TIMING – STANDBY PULSE
FIGURE 1-4: BUS TIMING – JITTER
SCIO
2
Data ‘0 Data ‘1 Data ‘0 Data ‘1 Data ‘0 Data ‘1 Data ‘0 Data ‘1 MAK bit NoSAK bit
1110
2
SCIO
7 8
Data ‘0 Data ‘1 Data ‘1 Data ‘0
12
SCIO
9
Standby
Mode
Ideal Edge
3
2
3 6 6
2
6 6
Ideal Edge Ideal Edge Ideal Edge
from Master from Master from Slave from Slave
2008-2016 Microchip Technology Inc. DS20002122D-page 5
11AA02E48/11AA02E64
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 11AA02EXX family of serial EEPROMs support
the UNI/O
®
protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC
®
microcontrollers, ASICs, or any other device with an
available discrete I/O line that can be configured
properly to match the UNI/O protocol.
The 11AA02EXX devices contain an 8-bit instruction
register. The devices are accessed via the SCIO pin.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master device which determines the clock period,
controls the bus access and initiates all operations,
while the 11AA02EXX works as slave. Both master
and slave can operate as transmitter or receiver, but
the master device determines which mode is active.
FIGURE 2-1: BLOCK DIAGRAM
SCIO
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Current-
Limited
Slope
Control
11AA02E48/11AA02E64
DS20002122D-page 6 2008-2016 Microchip Technology Inc.
3.0 BUS CHARACTERISTICS
3.1 Standby Pulse
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for T
STBY. At
this time, the 11AA02EXX will reset and return to
Standby mode. Subsequently, a high-to-low transition
on SCIO (the first low pulse of the header) will return
the device to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the
previous command. However, a period of T
SS must be
observed after the end of the command and before the
beginning of the start header. After TSS, the start
header (including T
HDR low pulse) can be transmitted
in order to begin the new command.
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must
perform a standby pulse before beginning a new
command, regardless of which device is to be selected
.
An example of two consecutive commands is shown in
Figure 3-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command, an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1: CONSECUTIVE COMMANDS EXAMPLE
3.2 Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of THDR, followed by transmitting an 8-bit ‘01010101
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
T
SS must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
FIGURE 3-2: START HEADER
Note: After a POR/BOR event occurs, a
low-to-high transition on SCIO must be
generated before proceeding with
communication, including a standby
pulse.
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
NoSAK
SAK
Standby Pulse
(1)
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
NoSAK
SAK
NoMAK
SAK
TSS
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
SCIO
Data ‘0 Data ‘1 Data0 Data ‘1 Data ‘0 Data ‘1 Data ‘0 Data ‘1 MAK NoSAKTSS THDR

11AA02E48-I/SN

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 2K, 256x8, 1.8V MAC Addressable
Lifecycle:
New from this manufacturer.
Delivery:
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