NB7N017M
http://onsemi.com
10
Table 11. AC CHARACTERISTICS V
CC
= 0 V; V
EE
= −3.465 V to −3.0 V or V
CC
= 3.0 V to 3.465 V; V
EE
=
0 V (Note 19)
Symbo
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
V
OUTPP
Output Voltage Amplitude @ B 2 Mode
f
in
= 3.5 GHz
(See Figure 5)
300 400 300 400 300 400 mV
t
PLH
,
t
PHL
Propagation Delay to Output Differential
CLK to TC
MR to TC
435
100
555
500
455
100
575
500
475
100
595
500
ps
t
JITTER
RMS Random Clock Jitter f
in
= 3.5 GHz
(See Figure 5)
2.5 3.0 3.0 ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 20)
100 2500 100 2500 100 2500 mV
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
25 45 65 25 45 65 25 45 65 ps
t
s
Setup Time Pa[7:0] to PLa
(Figure 23) Pb[7:0] to PLb
CE to CLK
SEL to CLK
PLa to CLK
PLb to CLK
Pa[7:0] to CLK
Pb[7:0] to CLK
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
ps
t
H
Hold Time PLa to Pa[7:0]
(Figure 23) PLb to Pb[7:0]
CLK to CE
CLK to SEL
CLK to PLa
CLK to PLb
CLK to PLb[7:0]
CLK to PLb[7:0]
−1500
−1250
450
0
−1750
−2250
−2250
−2000
−2700
−1900
40
−110
−1900
−2700
−3200
−2500
−1500
−1250
450
0
−1750
−2250
−2250
−2000
−2700
−1900
40
−110
−1900
−2700
−3200
−2500
−1500
−1250
450
0
−1750
−2250
−2250
−2000
−2700
−1900
40
−110
−1900
−2700
−3200
−2500
ps
t
SKEW
Device−to−Device (Note 21) 40 75 40 75 40 75 ps
t
PW
Minimum Pulse Width MR 250 85 250 85 250 85 ps
t
RR
Reset Recovery MR to CLK/CLK 3000 2500 3000 2500 3000 2500 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
19.Measured using a 400 mV source, 50% duty cycle clock source at f
in
= 1 GHz unless stated otherwise. All loading with 50 W to V
CC
. Input edge
rates 40 ps (20% − 80%).
20.V
INPP
(MAX) cannot exceed V
CC
− V
EE
.
21.Device−to−Device skew for identical transitions at identical V
CC
levels.
INPUT FREQUENCY (MHz)
Figure 5. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs. Input Frequency (f
in
)
@ Ambient Temperature (Typical)
OUTPUT VOLTAGE AMPLITUDE (mV)
JITTER
OUT
ps (RMS)
0
100
200
300
400
0 0.5 1 1.5 2 2.5 3 3.5 4
0
1
2
3
4
V
OUTPP
RMS Jitter
