NB7N017M
http://onsemi.com
16
Figure 15. Timing Diagram for SEL Input
(Before Critical Rising Edge of CLK)
MR
CLK
SEL
Pa[7:0]
Pb[7:0]
PLa
PLb
TC[7:0]
03
02
delay
d=4 d=4 d=4
d=3
Figure 16. Timing Diagram for SEL Input
(After Critical Rising Edge of CLK)
MR
CLK
SEL
Pa[7:0]
Pb[7:0]
PLa
PLb
TC[7:0]
03
02
delay
d=4 d=4 d=4 d=4 d=3
Figure 17. Timing Diagram Relating PLa, PLb, Pa(0:7), Pb(0:7)
MR
CLK
Pa[7:0]
PLa
Pa_INT[7:0]
Pb[7:0]
PLb
Pb_INT[7:0]
SEL
MUX_INT[7:0]
01 02 03 04 05 06 07 08
255 2 5 6 7
103 201 255 10 151 27 43 176
255 201 151 27 43
255 2 5
151
27 43
Pb/PLb have the same functionality as Pa/PLa
MUX_OUT is the output of the internal MUX
d=3
NB7N017M
http://onsemi.com
17
Figure 18. AC Reference Measurement
CLK
CLK
TC
TC
t
PHL
t
PLH
V
INPP
= V
IH
(CLK) − V
IL
(CLK)
V
OUTPP
= V
OH
(TC) − V
OL
(TC)
D
V
th
D
V
th
Figure 19. Differential Input Driven
Single−Ended
D
D
Figure 20. Differential Inputs Driven
Differentially
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
V
IHDmax
V
ILDmax
V
IHDmin
V
ILDmin
V
IHDtyp
V
ILDtyp
V
ID
= V
IHD
− V
ILD
V
CMR
V
CC
V
CMmax
V
CMmax
GND
Figure 21. V
th
Diagram Figure 22. V
CMR
Diagram
NB7N017M
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18
Figure 23. Setup and Hold Time
Setup Time
CLK
t
h
t
s
Hold Time
+
+
W
Receiver
Device
QD
50
W
50
Figure 24. Typical Termination for 16 mA Output Drive and Device Evaluation
Q D
V
CC
W
50
W
50
NB7N017M
V
CC
ORDERING INFORMATION
Device Package Shipping
NB7N017MMN QFN−52 260 Units / Tray
NB7N017MMNG QFN−52
(Pb−Free)
260 Units / Tray
NB7N017MMNR2 QFN−52 2000 / Tape & Reel
NB7N017MMNR2G QFN−52
(Pb−Free)
2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

NB7N017MMNR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Prescaler BBG 8BT DL MOD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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