NB7N017M
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6
CLK
CE
TC
8−BIT
COUNTER
MR
8−BIT REGa
MR
TC
GENERATOR
Figure 4. Block Diagram
PLa
TCLD MUX
SEL
8−BIT REGb
PLb
CLK
CE
SEL
TC
CLK_INT
GENERATOR
CLK_INT
CLK_INT
MR
DFF
Counter_State [7:0]
TC_INT
MUX_OUT[7:0]
Pb_INT[7:0]Pa_INT[7:0]
Pa[7:0] Pb[7:0]
Table 6. Interface Options
CLK INPUT interfacing options CLK INPUT INTERFACING OPTIONS
CML Connect VTCLK and VTCLK to V
CC
LVDS Connect VTCLK and VTCLK together
AC−COUPLED Bias VTCLK and VTCLK Inputs within (VIHCMR)
Common Mode Range
RSECL, PECL, NECL Standard ECL Termination Techniques or connect VTCLK and
VTCLK to V
TT
LVTTL, LVCMOS An Entered Voltage Should be Applied to the unused
Complementary Differential Input. Nominal Voltage is 1.5 V for
LVTTL and V
CC
/2 for LVCMOS Inputs.
Table 7. ATTRIBUTES
Characteristic Value
Internal Input Pulldown Resistor (MR, PLa, PLb) 75 k to V
EE
Internal Input Pullup Resistor (Pa[0:7], Pb[0:7]) 75 k to V
CC
ESD Protection Human Body Model
Machine Model
Charged Device Model
>500 V
>10 V
>2 kV
Moisture Sensitivity (Note 7) Pb Pkg Pb−Free Pkg
QFN−52 Level 2 Level 2
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 1914
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
7. For additional information, see Application Note AND8003/D.
