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9P935AFLFT

P1-P3P4-P6P7-P9P10-P12P13-P13
ICS9P935
IDT
TM
/ICS
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer ICS9P935 REV H 12/1/08
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
DATASHEET
1
FB_IN
SCLK
SDATA
CLK_INT
CLK_INC
Control
Logic
FB_OUT
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
PLL
Description
Output Features
DDR I/DDR II Zero Delay Clock Buffer
• Low skew, low jitter PLL clock driver
• Max frequency supported = 400MHz (DDRII 800)
•I
2
C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Programmable skew through SMBus
• Frequency defect control thorugh SMBus
• Individual output control programmable through SMBus
Funtional Block Diagram
Key Specifications
• CYCLE - CYCLE jitter: <100ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 48% - 52%
• 28-pin SSOP package
• Available in RoHS compliant packaging
• Operates @ 2.5V or 1.8V
Pin Configuration
DDRC0 1 28 GND
DDRT0 2 27 DDRC5
VDD2.5/1.8 3 26 DDRT5
DDRT1 4 25 VDD2.5/1.8
DDRC1 5 24 GND
GND 6 23 DDRC4
VDDA2.5/1.8 7 22 DDRT4
GND 8 21 VDD2.5/1.8
CLK_INT 9 20 SDATA
CLK_INC 10 19 SCLK
VDD2.5/1.8 11 18 FB_IN
DDRT2 12 17 FB_OUT
DDRC2 13 16 DDRT3
GND 14 15 DDRC3
28-SSOP/TSSOP
ICS9P935
IDT
TM
/ICS
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer ICS9P935 REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
2
Pin Description
Pin# Pin Name Type Pin Description
1 DDRC0 OUT "Complementary" Clock of differential pair output.
2 DDRT0 OUT "True" Clock of differential pair output.
3 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V
4 DDRT1 OUT "True" Clock of differential pair output.
5 DDRC1 OUT "Complementary" Clock of differential pair output.
6 GND PWR Ground pin.
7 VDDA2.5/1.8 PWR Output power supply, nominal 2.5V or 1.8V
8 GND PWR Ground pin.
9 CLK_INT IN "True" reference clock input.
10 CLK_INC IN "Complementary" reference clock input.
11 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V
12 DDRT2 OUT "True" Clock of differential pair output.
13 DDRC2 OUT "Complementary" Clock of differential pair output.
14 GND PWR Ground pin.
15 DDRC3 OUT "Complementary" Clock of differential pair output.
16 DDRT3 OUT "True" Clock of differential pair output.
17 FB_OUT OUT Feedback output, dedicated for external feedback.
18 FB_IN IN
Single-ended feedback input, provides feedback signal to internal PLL to eliminate
phase error with the input clock.
19 SCLK IN Clock pin of SMBus circuitry, 3.3V tolerant.
20 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant.
21 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V
22 DDRT4 OUT "True" Clock of differential pair output.
23 DDRC4 OUT "Complementary" Clock of differential pair output.
24 GND PWR Ground pin.
25 VDD2.5/1.8 PWR Power supply, nominal 2.5V or 1.8V
26 DDRT5 OUT "True" Clock of differential pair output.
27 DDRC5 OUT "Complementary" Clock of differential pair output.
28 GND PWR Ground pin.
IDT
TM
/ICS
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer ICS9P935 REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
3
Absolute Max
Supply Voltage -0.5V to 2.7V
Logic Inputs GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature 0°C to +70°C
Case Temperature 115°C
Storage Temperature –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current I
IH
V
I
= V
DD
or GND ±250 µA
Input Low Current I
IL
V
I
= V
DD
or GND ±10 µA
Output Disabled Low
Current
I
ODL
OE = L, V
ODL
= 100mV 100 µA
I
DD1. 8
C
L
= 0pf @ 100MHz 300 mA
I
DDLD
C
L
= 0pf 500 µA
Input Clamp Voltage V
IK
V
DDQ
= 1.8V Iin = -18mA -1.2
V
I
OH
= -100µA V
DD
-0.2 V
I
OH
= -9mA 1.1 V
I
OL
=100µA 0.1 V
I
OL
=9mA 0.6 V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
23pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
23pF
Operating Supply
Current
High-level output
voltage
V
OH
Low-level output voltage V
OL
P1-P3P4-P6P7-P9P10-P12P13-P13

9P935AFLFT

Mfr. #:
Buy 9P935AFLFT
Manufacturer:
IDT
Description:
Clock Buffer PC BUFFER
Lifecycle:
New from this manufacturer.
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