LTC3703-5
25
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MODE/SYNC Pin (External Synchronization)
The internal LTC3703-5 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2V
P-P
. The internal oscillator
locks to the external clock after the second clock transi-
tion is received. When external synchronization is de-
tected, LTC3703-5 will operate in forced continuous
mode. If an external clock transition is not detected for
three successive periods, the internal oscillator will revert
to the frequency programmed by the R
SET
resistor. The
internal oscillator can synchronize to frequencies be-
tween 100kHz and 600kHz, independent of the frequency
programmed by the R
SET
resistor. However, it is recom-
mended that an R
SET
resistor be chosen such that the
frequency programmed by the R
SET
resistor is close to the
expected frequency of the external clock. In this way, the
best converter operation (ripple, component stress, etc)
is achieved if the external clock signal is lost.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC3703-5 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
t
V
Vf
t
ON
OUT
IN
ON MIN
=>
()
where t
ON(MIN)
is typically 200ns.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3703-5 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t
ON(MIN)
for the same step-down ratio.
Pin Clearance/Creepage Considerations
The LTC3703-5 is available in two packages (GN16 and
G28) both with identical functionality. The GN16 package
gives the smallest size solution, however the 0.013”
(minimum) space between pins may not provide sufficient
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PC board trace clearance between high and low voltage
pins in higher voltage applications. Where clearance is an
issue, the G28 package should be used. The G28 package
has 4 unconnected pins between the all adjacent high
voltage and low voltage pins, providing 5(0.0106”) =
0.053” clearance which will be sufficient for most applica-
tions up to 60V. For more information, refer to the printed
circuit board design standards described in IPC-2221
(www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703-5 circuits: 1) LTC3703-5 V
CC
current,
2) MOSFET gate current, 3) I
2
R losses and 4) Topside
MOSFET transition losses.
1. V
CC
Supply current. The V
CC
current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703-5.
Total supply current is typically about 2.5mA and usually
results in a small (<1%) loss which is proportional to V
CC
.
2. DRV
CC
current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge Q
G
moves from DRV
CC
to
ground. The resulting dQ/dt is a current out of the DRV
CC
supply. In continuous mode, I
DRVCC
= f(Q
G(TOP)
+ Q
G(BOT)
),
where Q
G(TOP)
and Q
G(BOT)
are the gate charges of the top
and bottom MOSFETs.
3. I
2
R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
LTC3703-5
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MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with the
DCR resistance of L to obtain I
2
R losses. For example, if
each R
DS(ON)
= 25m and R
L
= 25m, then total resis-
tance is 50m. This results in losses ranging from 1% to
5% as the output current increases from 1A to 5A for a 5V
output.
4. Transition losses apply only to the topside MOSFET in
buck mode and they become significant when operating at
higher input voltages (typically 20V or greater). Transition
losses can be estimated from the second term of the P
MAIN
equation found in the Power MOSFET Selection section.
The transition losses can become very significant at the
high end of the LTC3703-5 operating voltage range. To
improve efficiency, one may consider lowering the fre-
quency and/or using MOSFETs with lower C
RSS
at the
expense of higher R
DS(ON)
.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, Schottky conduction losses during dead-time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703-5, the output accuracy due
to DC variations in input voltage and output load current
will be almost negligible. For the few cycles following a
load transient, however, the output deviation may be
larger while the feedback loop is responding. Consider a
typical 48V input to 5V output application circuit,
subjected to a 1A to 5A load transient. Initially, the loop is
in regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A (= 5A-1A) flows out of the
output capacitor while the inductor is still supplying only
1A. This sudden change will generate a (4A) • (R
ESR
)
voltage step at the output; with a typical 0.015 output
capacitor ESR, this is a 60mV step at the output.
The feedback loop will respond and will move at the band-
width allowed by the external compensation network
towards a new duty cycle. If the unity gain crossover fre-
quency is set to 50kHz, the COMP pin will get to 60% of the
way to 90% duty cycle in 3µs. Now the inductor is seeing
43V across itself for a large portion of the cycle and its
current will increase from 1A at a rate set by di/dt = V/L. If
the inductor value is 10µH, the peak di/dt will be 43V/10µH
or 4.3A/µs. Sometime in the next few micro-seconds after
the switch cycle begins, the inductor current will have
risen to the 5A level of the load current and the output
voltage will stop dropping. At this point, the inductor cur-
rent will rise somewhat above the level of the output cur-
rent to replenish the charge lost from the output capacitor
during the load transient. With a properly compensated
loop, the entire recovery time will be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple ca-
pacitors at the output. The capacitance value accounts for
the rest of the voltage drop until the inductor current rises.
With most output capacitors, several devices paralleled to
get the ESR down will have so much capacitance that this
drop term is negligible. Ceramic capacitors are an excep-
tion; a small ceramic capacitor can have suitably low ESR
with relatively small values of capacitance, making this
second drop term more significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC3703-5 to
recover after the output voltage has dropped due to a load
step. Optimizing loop compensation entails maintaining
the highest possible loop bandwidth while ensuring loop
stability. The feedback component selection section de-
scribes in detail the techniques used to design an opti-
mized Type 3 feedback loop, appropriate for most
LTC3703-5 systems.
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LTC3703-5
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Measurement Techniques
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gener-
ating a suitable transient to test the circuit. Output mea-
surements should be taken with a scope probe directly
across the output capacitor. Proper high frequency prob-
ing techniques should be used. In particular, don’t use the
6" ground lead that comes with the probe! Use an adapter
that fits on the tip of the probe and has a short ground clip
to ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703-5 and the transient generator
must be minimized.
Figure 19 shows an example of a simple transient genera-
tor. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC3703-5
circuits. Solder the MOSFET and the resistor(s) as close to
the output of the LTC3703-5 circuit as possible and set up
the signal generator to pulse at a 100Hz rate with a 5% duty
cycle. This pulses the LTC3703-5 with 500µs
transients10ms apart, adequate for viewing the entire
transient recovery time for both positive and negative
transitions while keeping the load resistor cool.
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 20V to 60V (48V nominal), V
OUT
=
12V ±5%, I
OUT(MAX)
= 10A, f=250kHz. First, calculate R
SET
to give the 250kHz operating frequency:
R
SET
= 7100/(250-25) = 31.6k
Next, choose the inductor value for about 40% ripple
current at maximum V
IN
:
L
V
kHz A
H=
12
250 0 4 10
1
12
60
10
( )( . )( )
With 10µH inductor, ripple current will vary from 1.9A to
3.8A (19% to 38%) over the input supply range.
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum V
IN
:
t
V
V f kHz
ns
ON MIN
OUT
IN MIN
()
()
() ( )
== =
12
60 250
800
which is above the LTC3703-5’s 200ns minimum on-time.
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
60V(max) plus any ringing, choose a 60V MOSFET.
Si7850DP has a 60V BV
DSS
, R
DS(ON)
= 22m(max), δ =
0.007/°C, C
MILLER
= (9nC – 3nC)/30V = 200pF, V
GS(MILLER)
= 3.8V, θ
JA
= 20°C/W. The power dissipation can be
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Figure 19. Transient Load Generator
LTC3703-5
V
OUT
IRFZ44 OR
EQUIVALENT
R
LOAD
50
0V TO 10V
100Hz, 5%
DUTY CYCLE
LOCATE CLOSE TO THE OUTPUT
37035 F19
PULSE
GENERATOR

LTC3703IG-5#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Lower Voltage Gate-Drive & Supply Version of LTC3703
Lifecycle:
New from this manufacturer.
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