LTC3703IG-5#TRPBF Datasheet LTC3703IG-5#PBF, LTC3703EG-5#TRPBF, LTC3703IG-5#TRPBF | P7-P9

LTC3703-5

37035fa

MODE/SYNC

(Pin 1/Pin 6): Pulse Skip Mode Enable/Sync

Pin. This multifunction pin provides Pulse Skip Mode en-

able/disable control and an external clock input for synchro-

nization of the internal oscillator. Pulling this pin below 0.8V

or to an external logic-level synchronization signal disables

Pulse Skip Mode operation and forces continuous opera-

tion. Pulling the pin above 0.8V enables Pulse Skip Mode

operation. This pin can also be connected to a feedback

resistor divider from a secondary winding on the inductor

to regulate a second output voltage.

SET

(Pin 2/Pin 7): Frequency Set. A resistor connected to

this pin sets the free running frequency of the internal os-

cillator. See applications section for resistor value selec-

tion details.

COMP (Pin 3/Pin 8): Loop Compensation. This pin is con-

nected directly to the output of the internal error amplifier.

An RC network is used at the COMP pin to compensate the

feedback loop for optimal transient response.

FB (Pin 4/Pin 9): Feedback Input. Connect FB through a

resistor divider network to V

OUT

to set the output voltage.

Also connect the loop compensation network from COMP

to FB.

MAX

(Pin 5/Pin 10): Current Limit Set. The I

MAX

pin sets

the current limit comparator threshold. If the voltage drop

across the bottom MOSFET exceeds the magnitude of the

voltage at I

MAX

, the controller goes into current limit. The

MAX

pin has an internal 12µA current source, allowing the

current threshold to be set with a single external resistor

to ground. See the Current Limit Programming section for

more information on choosing R

IMAX

INV (Pin 6/Pin 11): Top/Bottom Gate Invert. Pulling this pin

above 2V sets the controller to operate in step-up (boost)

mode with the TG output driving the synchronous MOSFET

and the BG output driving the main switch. Below 1V, the

controller will operate in step-down (buck) mode.

RUN/SS (Pin 7/Pin 13): Run/Soft-Start. Pulling RUN/SS be-

low 0.9V will shut down the LTC3703-5, turn off both of the

external MOSFET switches and reduce the quiescent sup-

ply current to 25µA. A capacitor from RUN/SS to ground

will control the turn-on time and rate of rise of the output

voltage at power-up. An internal 4µA current source pull-

up at the RUN/SS pin sets the turn-on time at approximately

750ms/µF.

GND (Pin 8/Pin 14): Ground Pin.

BGRTN (Pin 9/Pin 15): Bottom Gate Return. This pin con-

nects to the source of the pull-down MOSFET in the BG

driver and is normally connected to ground. Connecting a

negative supply to this pin allows the synchronous

MOSFET’s gate to be pulled below ground to help prevent

false turn-on during high dV/dt transitions on the SW node.

See the Applications Information section for more details.

BG (Pin 10/Pin 19): Bottom Gate Drive. The BG pin drives

the gate of the bottom N-channel synchronous switch

MOSFET. This pin swings from BGRTN to DRV

DRV

(Pin 11/Pin 20): Driver Power Supply Pin. DRV

provides power to the BG output driver. This pin should be

connected to a voltage high enough to fully turn on the

external MOSFETs, normally 4.5V to 15V for logic level

threshold MOSFETs. DRV

should be bypassed to BGRTN

with a 10µF, low ESR (X5R or better) ceramic capacitor.

(Pin 12/Pin 21) :

Main Supply Pin. All internal circuits

except the output drivers are powered from this pin. V

should be connected to a low noise power supply voltage

between 4.5V and 15V and should be bypassed to GND

(Pin 8) with at least a 0.1µF capacitor in close proximity to

the LTC3703-5.

SW (Pin 13/Pin 26): Switch Node Connection to Inductor

and Bootstrap Capacitor. Voltage swing at this pin is from

a Schottky diode (external) voltage drop below ground to

TG (Pin 14/Pin 27): Top Gate Drive. The TG pin drives the

gate of the top N-channel synchronous switch MOSFET. The

TG driver draws power from the BOOST pin and returns to

the SW pin, providing true floating drive to the top MOSFET.

BOOST (Pin 15/Pin 28): Top Gate Driver Supply. The BOOST

pin supplies power to the floating TG driver. The BOOST pin

should be bypassed to SW with a low ESR (X5R or better)

0.1µF ceramic capacitor. An additional fast recovery Schot-

tky diode from DRV

to BOOST will create a complete float-

ing charge-pumped supply at BOOST.

(Pin 16/Pin 1):

Input Voltage Sense Pin. This pin is con-

nected to the high voltage input of the regulator and is used

by the internal feedforward compensation circuitry to im-

prove line regulation. This is not a supply pin.

PI FU CTIO S

(GN16/G28)

LTC3703-5

37035fa

FU CTIO AL DIAGRA

UVSD OTSD

CHIP

3.2V

4µA

RUN/SS

BANDGAP

SYNC

DETECT

OVER

TEMP

UVLO

OSC

% DC

LIMIT

DRIVE

LOGIC

–

EXT SYNC

FORCED CONTINUOUS

–

0.8V

MODE/SYNC

COMP

(<15V)

INV

PWM

MIN MAX

0.76V

0.84V

OVERCURRENT

12µA

50mV

MAX

BOOST

DRV

BGRTN

INV

GND

GN16

OT SD 0.8V

REFERENCE

INTERNAL

3.2V V

UV SD

FSET

37035 FD

REVERSE

CURRENT

RSET

VCC

OUT

INV

OPERATIO

(Refer to Functional Diagram)

The LTC3703-5 is a constant frequency, voltage mode

controller for DC/DC step-down converters. It is designed

to be used in a synchronous switching architecture with

two external N-channel MOSFETs. Its high operating volt-

age capability allows it to directly step down input voltages

up to 60V without the need for a step-down transformer.

For circuit operation, please refer to the Functional

Diagram of the IC and the circuit on the first page of this

data sheet. The LTC3703-5 uses voltage mode control in

which the duty ratio is controlled directly by the error

amplifier output and thus requires no current sense resis-

tor. The V

pin receives the output voltage feedback and

is compared to the internal 0.8V reference by the error

amplifier, which outputs an error signal at the COMP pin.

LTC3703-5

37035fa

OPERATIO

(Refer to Functional Diagram)

When the load current increases, it causes a drop in the

feedback voltage relative to the reference. The COMP volt-

age then rises, increasing the duty ratio until the output

feedback voltage again matches the reference voltage. In

normal operation, the top MOSFET is turned on when the

RS latch is set by the on-chip oscillator and is turned off

when the PWM comparator trips and resets the latch. The

PWM comparator trips at the proper duty ratio by compar-

ing the error amplifier output (after being “compensated”

by the line feedforward multiplier) to a sawtooth waveform

generated by the oscillator. When the top MOSFET is turned

off, the bottom MOSFET is turned on until the next cycle

begins or, if Pulse Skip Mode operation is enabled, until

the inductor current reverses as determined by the reverse

current comparator. MAX and MIN comparators ensure

that the output never exceed ±5% of nominal value by

monitoring V

and forcing the output back into regulation

quickly by either keeping the top MOSFET off or forcing

maximum duty cycle. The operation of its other features—

fast transient response, outstanding line regulation, strong

gate drivers, short-circuit protection, and shutdown/

soft-start—are described below.

Fast Transient Response

The LTC3703-5 uses a fast 25MHz op amp as an error am-

plifier. This allows the compensation network to be opti-

mized for better load transient response. The high

bandwidth of the amplifier, along with high switching fre-

quencies and low value inductors, allow very high loop

crossover frequencies. The 800mV internal reference allows

regulated output voltages as low as 800mV without exter-

nal level shifting amplifiers.

Line Feedforward Compensation

The LTC3703-5 achieves outstanding line transient re-

sponse using a patented feedforward correction scheme.

With this circuit the duty cycle is adjusted instantaneously

to changes in input voltage, thereby avoiding unaccept-

able overshoot or undershoot. It has the added advantage

of making the DC loop gain independent of input voltage.

Figure 1 shows how large transient steps at the input have

little effect on the output voltage.

20µs/DIV

OUT

50mV/DIV

AC COUPLED

OUT

= 12V

LOAD

= 1A

25V TO 60V V

STEP

20V/DIV

2A/DIV

37035 F01

Figure 1. Line Transient Performance

Strong Gate Drivers

The LTC3703-5 contains very low impedance drivers

capable of supplying amps of current to slew large MOSFET

gates quickly. This minimizes transition losses and allows

paralleling MOSFETs for higher current applications. A

60V floating high side driver drives the top side MOSFET

and a low side driver drives the bottom side MOSFET (see

Figure 2). They can be powered from either a separate DC

supply or a voltage derived from the input or output

voltage (see MOSFET Driver Supplies section). The bot-

tom side driver is supplied directly from the DRV

pin.

The top MOSFET drivers are biased from floating boot-

strap capacitor C

, which normally is recharged during

each off cycle through an external diode from DRV

when

the top MOSFET turns off. In Pulse Skip Mode operation,

where it is possible that the bottom MOSFET will be off for

an extended period of time, an internal counter guarantees

that the bottom MOSFET is turned on at least once every

10 cycles for 10% of the period to refresh the bootstrap

capacitor. An undervoltage lockout keeps the LTC3703-5

shut down unless this voltage is above 4.1V.

The bottom driver has an additional feature that helps

minimize the possibility of external MOSFET shoot-thru.

When the top MOSFET turns on, the switch node dV/dt

pulls up the bottom MOSFET’s internal gate through the

Miller capacitance, even when the bottom driver is holding

the gate terminal at ground. If the gate is pulled up high

enough, shoot-thru between the top side and bottom side

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LTC3703IG-5#TRPBF

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Lower Voltage Gate-Drive & Supply Version of LTC3703

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LTC3703IG-5#TRPBF

LTC3703IG-5#TRPBF

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