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8705BYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I
DATA SHEETNot Recommend for New Designs
8705I REVISION E 7/13/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 8705I is a highly versatile 1:8 Differential-to-LVCMOS/
LVTTL Clock Generator. The 8705I has two selectable clock
inputs. The CLK1, nCLK1 pair can accept most standard
differential input levels. The single ended CLK0 input accepts
LVCMOS or LVTTL input levels.The 8705I has a fully integrated
PLL and can be confi gured as zero delay buffer, multiplier
or divider and has an input and output frequency range of
15.625MHz to 250MHz. The reference divider, feedback divider
and output divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
FEATURES
• Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with confi gurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
• Not Recommended for New Designs
For new designs, contact IDT.
BLOCK DIAGRAM PIN ASSIGNMENT
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
2 REVISION E 7/13/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 2 SEL0, SEL1 Input Pulldown
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
3 CLK0 Input Pulldown Clock input. LVCMOS/LVTTL interface levels.
4 nc No connect.
5 CLK1 Input Pulldown Non-inverting differential clock input.
6 nCLK1 Input Pullup Inverting differential clock input.
7 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects differential CLK1, nCLK1. When
LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels.
8 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal divid-
ers and the outputs are enabled. LVCMOS/LVTTL interface levels
9, 32 V
DD
Power Core supply pins.
10 FB_IN Input Pulldown
LVCMOS/LVTTL feedback input to phase detector for regenerating
clocks with “zero delay”. Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
11 SEL2 Input Pulldown
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
12, 16, 20, 24,
28
V
DDO
Power Output supply pins.
13, 15, 17, 19,
21, 23, 25, 27
Q0, Q1, Q2,
Q3, Q4, Q5,
Q6, Q7
Output
Clock output. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
14, 18, 22, 26 GND Power Power supply ground.
29 SEL3 Input Pulldown
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
30 V
DDA
Power Analog supply pin.
31 PLL_SEL Input Pullup
Selects between the PLL and reference clock as input to the dividers.
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
KΩ
R
PULLDOWN
Input Pulldown Resistor 51
KΩ
C
PD
Power Dissipation Capacitance
(per output)
V
DD
, V
DDA
, V
DDO
= 3.465V 23 pF
R
OUT
Output Impedance 5 7 12
Ω
REVISION E 7/13/15
8705I DATA SHEET
3 Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
TABLE 3A. PLL ENABLE FUNCTION TABLE
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3 SEL2 SEL1 SEL0 Q0:Q7
0000 ÷ 8
0001 ÷ 8
0010 ÷ 8
0 0 1 1 ÷ 16
0 1 0 0 ÷ 16
0 1 0 1 ÷ 16
0 1 1 0 ÷ 32
0 1 1 1 ÷ 32
1 0 0 0 ÷ 64
1 0 0 1 ÷ 128
1010 ÷ 4
1011 ÷ 4
1100 ÷ 8
1101 ÷ 2
1110 ÷ 4
1111 ÷ 2
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q0:Q7
0 0 0 0 125 - 250 ÷ 1
0 0 0 1 62.5 - 125 ÷ 1
0 0 1 0 31.25 - 62.5 ÷ 1
0 0 1 1 15.625 -31.25 ÷ 1
0 1 0 0 125 - 250 ÷ 2
0 1 0 1 62.5 - 125 ÷ 2
0 1 1 0 31.25 - 62.5 ÷ 2
0 1 1 1 125 - 250 ÷ 4
1 0 0 0 62.5 - 125 ÷ 4
1 0 0 1 125 - 250 ÷ 8
1 0 1 0 62.5 - 125 x 2
1 0 1 1 31.25 - 62.5 x 2
1 1 0 0 15.625 - 31.25 x 2
1 1 0 1 31.25 - 62.5 x 4
1 1 1 0 15.625 - 31.25 x 4
1 1 1 1 15.625 - 31.25 x 8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8705BYILFT

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Manufacturer:
IDT
Description:
Clock Generators & Support Products 8 LVCMOS OUT MUX MULT/DIV
Lifecycle:
New from this manufacturer.
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