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8705BYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
4 REVISION E 7/13/15
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 90 mA
I
DDA
Analog Supply Current 15 mA
I
DDO
Output Supply Current 20 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input
High Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
2V
DD
+ 0.3 V
CLK0 2 V
DD
+ 0.3 V
V
IL
Input
Low Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
-0.3 0.8 V
CLK0 -0.3 1.3 V
I
IH
Input
High Current
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
DD
= V
IN
= 3.465V 150 µA
PLL_SEL V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input
Low Current
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
DD
= 3.465V, V
IN
= 0V -5 µA
PLL_SEL V
DD
= 3.465V, V
IN
= 0V -150 µA
V
OH
Output High Voltage; NOTE 1 2.6 V
V
OL
Output Low Voltage; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. In the Parameter Measurement Information section,
see “3.3V Output Load Test Circuit” fi gure.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
REVISION E 7/13/15
8705I DATA SHEET
5 Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 15.625 250 MHz
tp
LH
Propagation Delay,
Low-to-High; NOTE 1
CLK0
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
57ns
CLK1, nCLK1
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
5 7.3 ns
t(Ø)
Static Phase Offset;
NOTE 2, 4
CLK0
PLL_SEL = 3.3V,
fREF ≤ 200MHz, Qx ÷ 1
-100 25 150 ps
CLK1, nCLK1
PLL_SEL = 3.3V,
fREF ≤ 167MHz, Qx ÷ 1
-15 +135 285 ps
PLL_SEL = 3.3V,
fREF = 200MHz, Qx ÷ 1
-50 +100 250 ps
tsk(o)
Output Skew;
NOTE 3, 4
CLK0 PLL_SEL = 0V 65 ps
CLK1, nCLK1 PLL_SEL = 0V 55 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f
OUT
> 40MHz 45 ps
t
L
PLL Lock Time 1mS
t
R
Output Rise Time 400 950 ps
t
F
Output Fall Time 400 950 ps
odc Output Duty Cycle 43 57 %
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defi ned as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK1 V
DD
= V
IN
= 3.465V 150 µA
nCLK1 V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input Low Current
CLK1 V
DD
= 3.465V, V
IN
= 0V -5 µA
nCLK1 V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5 V
DD
- 0.85 V
NOTE 1: Common mode voltage is defi ned as
V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is
V
DD
+ 0.3V.
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
6 REVISION E 7/13/15
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 2.375 2.5 2.625 V
V
DDA
Analog Supply Voltage 2.375 2.5 2.625 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 90 mA
I
DDA
Analog Supply Current 15 mA
I
DDO
Output Supply Current 20 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input
High Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
2V
DD
+ 0.3 V
CLK0 2 V
DD
+ 0.3 V
V
IL
Input
Low Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
-0.3 0.8 V
CLK0 -0.3 1.3 V
I
IH
Input
High Current
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
DD
= V
IN
= 2.625V 150 µA
PLL_SEL V
DD
= V
IN
= 2.625V 5 µA
I
IL
Input
Low Current
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
DD
= 2.625V, V
IN
= 0V -5 µA
PLL_SEL V
DD
= 2.625V, V
IN
= 0V -150 µA
V
OH
Output High Voltage; NOTE 1 1.8 V
V
OL
Output Low Voltage; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. In the Parameter Measurement Information section,
see “2.5V Output Load Test Circuit” fi gure.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK1 V
DD
= V
IN
= 2.625V 150 µA
nCLK1 V
DD
= V
IN
= 2.625V 5 µA
I
IL
Input Low Current
CLK1 V
DD
= 2.625V, V
IN
= 0V -5 µA
nCLK1 V
DD
= 2.625V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
GND + 0.5 V
DD
- 0.85 V
NOTE 1: Common mode voltage is defi ned as
V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is
V
DD
+ 0.3V.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8705BYILFT

Mfr. #:
Buy 8705BYILFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 8 LVCMOS OUT MUX MULT/DIV
Lifecycle:
New from this manufacturer.
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