REVISION E 7/13/15
8705I DATA SHEET
17 Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
B
3A
5A
5B
3
5
7
PLL Enable Function Table - revised the Reference Frequency Range column
3.3V AC Characteristics Table - updated the Output Frequency row from
275MHz Max. to 250MHz Max.
2.5V AC Characteristics Table - updated the Output Frequency row from
275MHz Max. to 250MHz Max.
4/5/02
B 1 2 Pin Description Table - revised power pin descriptions. 4/10/02
B
22
Pin Characteristics Table - added 23pF to C
PD
row. 7/15/02
B1 2
Pin Description Table - Pin# 10 from description, replaced “Connect to pin 10.”
with “Connect to one of the outputs.”
8/1/02
B1
2
8
Revised CLK0 description and MR description.
Revised Output Rise/Fall Time Diagram.
8/21/02
C
1
4A & 4D
5A & 5B
2
4 & 6
5 & 7
Pin Description table - revised MR and V
DD
descriptions.
Power Supply Table - changed V
DD
parameter to correspond with the pin de-
scription.
AC tables - Changed the Static Phase Offset limits for CLK1, nCLK1.
1/22/03
D
T5B 7
9
2.5V AC Characteristics Table - added Phase Jitter spec, and Note 5.
Replaced Static Phase Offset Diagram with Phase Jitter & SPO Diagram.
3/14/03
D
T2 2
11
12 & 13
Pin Characteristics Table - changed C
IN
4pF max. to 4pF typical.
R
OUT
, added 5W min. and 12W max.
Added Differential Clock Input Interface section.
Added Layout Guideline and PCB Board Layout.
7/14/03
D
T8
1
16
Added Lead-Free bullet to Features section.
Added Lead-Free part number to Ordering Information table.
7/8/04
E
T8 16
18
Updated datasheet’s header/footer with IDT from ICS.
Removed “”ICS”” prefi x from Part/Order Number column. Corrected packaging
column
Added Contact Page.
7/16/10
E 1 NRND - Nor Recommended For New Designs 5/30/13
E
T8 16 Ordering Information - removed leaded devices.
Updated data sheet format
7/13/15
