REVISION E 7/13/15
8705I DATA SHEET
7 Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
TABLE 5B. AC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 15.625 250 MHz
tp
LH
Propagation Delay,
Low-to-High; NOTE 1
CLK0
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
57ns
CLK1, nCLK1
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
5 7.3 ns
t(Ø)
Static Phase Offset;
NOTE 2, 4
CLK0
PLL_SEL = 2.5V,
fREF ≤ 200MHz, Qx ÷ 1
-250 25 200 ps
CLK1, nCLK1
PLL_SEL = 2.5V,
fREF = 133MHz, Qx ÷ 1
-50 100 250 ps
PLL_SEL = 2.5V,
fREF = 200MHz, Qx ÷ 1
-100 +100 300 ps
tsk(o)
Output Skew;
NOTE 3, 4
CLK0 PLL_SEL = 0V 65 ps
CLK1, nCLK1 PLL_SEL = 0V 55 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f
OUT
> 40MHz 45 ps
tjit(q) Phase Jitter; NOTE 4, 5
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
±50 ps
t
L
PLL Lock Time 1mS
t
R
Output Rise Time 400 950 ps
t
F
Output Fall Time 400 950 ps
odc Output Duty Cycle 43 57 %
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defi ned as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 5: Phase jitter is dependent on the input source used.
