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8735BMI-21LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
DATA SHEET
700MHz, Differential-to-3.3V LVPECL
Zero Delay Clock Generator
8735BI-21
8735BI-21 REVISION 1 1/27/15 1 ©2015 Integrated Device Technology, Inc.
General Description
8735BI-21
V
cco
nc
nQFB
QFB
nQ
Q
nc
V
CCO
nc
V
CC
nc
nc
SEL3
V
EE
PLL_SEL
V
CCA
MR
nc
nCLK
CLK
nc
nc
SEL1
SEL0
V
CC
nc
nFB_IN
FB_IN
SEL2
V
EE
nc
nc
9
10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
32
31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
QFB
nFB_IN
V
CC
MR
nCLK
CLK
nQFB
V
EE
SEL2
FB_IN
nQ
PLL_SEL
V
CC
SEL0
SEL1
nc
Q
V
CCO
SEL3
V
CCA
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
8735BI-21
20-pin, 7.5mm x 12.8mm X 2.3MM SOIC Package
32-pin, 5mm x 5mm X 0.925MM VFQFN Package
The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL
clock generator. The CLK, nCLK pair can accept most standard
differential input levels. The 8735BI-21 has a fully integrated PLL and
can be configured as zero delay buffer, multiplier or divider, and has
an output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is
routed around the PLL and into the internal output dividers.
Pin Assignment
Features
• One differential 3.3V LVPECL output pair, one differential feedback
output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels:
L
VDS, LVPECL, LVHSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration with
config
urable frequencies
• Cycle-to-cycle jitter: 50ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient o
perating temperature
• Available in RoHS compliant package
Block Diagram
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q
nQ
QFB
nQFB
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
8735BI-21 DATA SHEET
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
2 REVISION 1 1/27/15
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
1
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Ta ble 2 , Pin Characteristics, for typical values.
Name Type Description
CLK Input Pulldown Non-inverting differential clock input.
nCLK Input Pullup Inverting differential clock input.
nFB_IN Input Pullup
Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to nQFB.
FB_IN Input Pulldown
Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to QFB.
MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the
true outputs Q and QFB to go low and the inverted outputs nQ and nQFB to go high. When
LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
SEL0, SEL1,
SEL2, SEL3
Input Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
PLL_SEL Input Pullup
Selects between the PLL and reference clock as the input to the dividers. When LOW,
selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
nQ, Q Output Differential feedback outputs. LVPECL interface levels.
nQFB, QFB Output Differential feedback outputs. LVPECL interface levels.
V
EE
Power Negative supply.
V
CC
Power Core supply.
V
CCA
Power Analog supply.
V
CCO
Power Output supply.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance IN, nIN 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
REVISION 1 1/27/15 3 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Table 3A. Control Input Function Table
1
NOTE 1: VCO frequency range for all configurations above is 250MHz to 700MHz.
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q, nQ; QFB, nQFB
0000 250-700 ÷ 1 (default)
0001 125 - 350 ÷ 1
0010 62.5 - 175 ÷ 1
0011 31.25 - 87.5 ÷ 1
0100 250 - 700 ÷ 2
0101 125 - 350 ÷ 2
0110 62.5 - 175 ÷ 2
0111 250 - 700 ÷ 4
1000 125 - 350 ÷ 4
1001 250 - 700 ÷ 8
1010 125 - 350 x 2
1011 62.5 - 175 x 2
1100 31.25 - 87.5 x 2
1101 62.5 - 175 x 4
1110 31.25 - 87.5 x 4
1111 31.25 - 87.5 x 8
Table 3B. PLL Bypass Function Table
1
NOTE 1: VCO frequency range for all configurations above is 250MHz to 700MHz.
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3SEL2 SEL1 SEL0 Q, nQ; QFB, nQFB
0 0 0 0 ÷ 4 (default)
0001 ÷ 4
0010 ÷ 4
0011 ÷ 8
0100 ÷ 8
0101 ÷ 8
0110 ÷ 16
0111 ÷ 16
1000 ÷ 32
1001 ÷ 64
1010 ÷ 2
1011 ÷ 2
1100 ÷ 4
1101 ÷ 1
1110 ÷ 2
1111 ÷ 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8735BMI-21LFT

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Buy 8735BMI-21LFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 700MHz, Differential 3.3V LVPECL Zero
Lifecycle:
New from this manufacturer.
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