REVISION 1 1/27/15 13 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8735BI-21.
Equations and example calculations are also provided.
Max I
CC_MA
at worst case:
85°C = 133mA
1. Power Dissipation.
The total power dissipation for the 8735BI-21 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
• Power (core)
MAX
= V
CC_MAX
* I
CC_MAX
= 3.465V * 155mA = 537mW
• Power (outputs)
MAX
= 30mW/Loaded output pair
If all outputs are loaded, the total power is 2 * 30mW = 60m
W
Total Power_
MAX
= (3.465V, with all outputs switching) = 537mW + 60mW = 597mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature
at the junction of the bond wire and bond pad directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures
that the bond wire and bond pad temperature remains be
low 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 46.2°C/W per Table 7A, and 33.1°C/W per Table 7B below:
Therefore, Tj for an ambient temperature of 85°C with all outputs switching for 20-Lead SOIC i
s:
85°C + 0.597W * 46
.2°C/W = 112.6°C. This is below the limit of 125°C.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching for 32-Lead VFQFN is:
85°C + 0.597W * 33
.1°C/W = 104.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depe
nding on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance
JA
for 20 Lead SOIC, Forced Convection
JA
vs. Air Flow
Linear Feet per Minute 0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
Table 7B. Thermal Resistance
JA
for 32 Lead VFQFN, Forced Convection
JA
by Velocity
Meters per Second 013
Multi-Layer PCB, JEDEC Standard Test Boards 33.1°C/W 28.1°C/W 25.4°C/W
