8735BI-21 DATA SHEET
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
6 REVISION 1 1/27/15
AC Electrical Characteristics
Table 6. Input Frequency Characteristics, V
CC
= V
CCO
= 3.3V ±5%, T
A
= 0°C to 85°C
1
NOTE 1: All parameters measured at f
OUT
unless noted otherwise.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 700 MHz
t
PD
Propagation Delay
2
NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.
PLL_SEL = 0V, f 700MHz 2.8 4.9 ns
tsk(o) Output Skew
3, 4
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
PLL_SEL = 0V 35 ps
t(Ø) Static Phase Offset
4, 5
NOTE 5: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
PLL_SEL = 3.3V -100 200 ps
tjit(cc) Cycle-to-Cycle Jitter
4, 6
NOTE 6: Characterized at VCO frequency of 622MHz,.
50 ps
tjit() Phase Jitter
4, 6, 7
NOTE 7: Phase jitter is dependent on the input source used.
±80 ps
t
L
PLL Lock Time 1ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% @ 50MHz 200 700 ps
odc Output Duty Cycle f
OUT
250MHz 47 53 %
