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6048C–ATARM–29-Jun-06
AT91SAM7A1
16. Capture Module (CAPT)
The capture module is a frame analyzer. It stores the period of time between two edges of a sig-
nal in a register. This period is described as a number of counter cycles. The capture allows data
transfers with the PDC.
17. Pulse Width Modulator (PWM)
The AT91SAM7A1 includes four PWM channels. Each channel can generate pulses. The fre-
quency and the duty cycle of each channel can be configured.
18. Watch Timer (WT)
The watch timer provides a seconds counter and an alarm function. The alarm register has a
resolution of 30.5 µs. This allows a 32-bit register to have sufficient range to cater for a 24 or 36
hour period.
19. Watchdog (WD)
The AT91SAM7A1 has an internal watchdog that can be used to prevent system lock-up if the
software becomes trapped in a deadlock.
20. Special Function Module (SFM)
The AT91SAM7A1 provides registers which implement the following special functions:
• Chip identification
• RESET status
21. Analog-to-digital Converter (ADC)
The 8-channel, 10-bit Analog-to-Digital Converter (ADC) is based on a Successive Approxima-
tion Register (SAR) approach. The ADC has eight analog input pins, ANA0IN0 to ANA0IN7, and
provides an interrupt signal to the AIC. The ADC has two dedicated analog power supply pins,
VDDANA and GND, and the input reference voltage pin, VREFP. Each channel can be enabled
or disabled independently, and has its own data register. The ADC can be configured to auto-
matically enter Sleep Mode after a conversion sequence, and can be triggered by the software.
The ADC allows a data transfer with the PDC.
22. Power Management Controller (PMC)
The AT91SAM7A1 Power Management Controller allows optimization of power consumption.
The PMC enables/disables the clock inputs of PDC and ARM core. Moreover, the main oscilla-
tor, the PLL and the analog peripherals can be put in standby mode, allowing minimum power
consumption to be obtained. The PMC provides the following operating modes:
• Normal: Clock generator provides clock to chip
• Wait mode: ARM core clock is deactivated
• Slow mode: clock generator is deactivated, the system is clocked at 32.768 kHz
Each peripheral clock can be independently stopped or started directly in the peripheral to fur-
ther reduce power consumption in Normal, Wait and Slow Modes.
