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AT91SAM7A1-AU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4
6048C–ATARM–29-Jun-06
AT91SAM7A1
3. Pin Configuration
Notes: 1. Pins 7, 28 and 43 are connected internally.
2. Pins 6, 27 and 127 are connected internally.
Table 3-1. Pin Configuration
Pin Name Pad Pin Name Pad Pin Name Pad Pin Name Pad
1 D0 PC3B01D 37 ADD11 PC3T02 73 GND 109 ANA0IN1 AIMUX1
2 D8 PC3B01D 38 ADD12 PC3T02 74 PIOA2 MC5B04 110 ANA0IN2 AIMUX1
3 D1 PC3B01D 39 ADD13 PC3T02 75 PIOA3 MC5B04 111 ANA0IN3 AIMUX1
4 D9 PC3B01D 40 ADD14 PC3T02 76 VDDIO 112 ANA0IN4 AIMUX1
5 VDDCORE 41 ADD15 PC3T02 77 PIOA4 MC5B03 113 ANA0IN5 AIMUX1
6GND
(2)
42 GND 78 PIOA5 MC5B03 114 ANA0IN6 AIMUX1
7 VDDCORE
(1)
43 VDDCORE
(1)
79 PIOA6 MC5B03 115 ANA0IN7 AIMUX1
8 D2 PC3B01D 44 VDDIO 80 PIOA7 MC5B03 116 GND
9 D10 PC3B01D 45 IRQ0 MC5D00 81 PIOA8 MC5B03 117 VDDCORE
10 D3 PC3B01D 46 FIQ MC5D00 82 PIOA9 MC5B03 118 MCKI OSC16M
11 D11 PC3B01D 47 T0TIOA0/MPIO MC5B01 83 GND 119 MCKO OSC16M
12 D4 PC3B01D 48 T0TIOB0/MPIO MC5B01 84 PIOA10 MC5B02 120 PLLRC PLL080M1
13 D12 PC3B01D 49 T0TCLK0/MPIO MC5B01 85 PIOA11 MC5B02 121 GND
14 D5 PC3B01D 50 T0TIOA1/MPIO MC5B01 86 PIOA12 MC5B01 122 VDDCORE
15 D13 PC3B01D 51 T0TIOB1/MPIO MC5B01 87 PIOA13 MC5B01 123 RTCKI OSC33K
16 D6 PC3B01D 52 T0TCLK1/MPIO MC5B01 88 PIOA14 MC5B01 124 RTCKO OSC33K
17 D14 PC3B01D 53 T0TIOA2/MPIO MC5B01 89 PIOA15 MC5B01 125 GND
18 D7 PC3B01D 54 T0TIOB2/MPIO MC5B01 90 PIOA16 MC5B01 126 VDDIO
19 D15 PC3B01D 55 GND 91 PIOA17 MC5B01 127 GND
(2)
20 ADD17 PC3T02 56 T0TCLK2/MPIO MC5B01 92 PWM0/MPIO MC5B01 128 GND
21 ADD16 PC3T02 57 TXD0/MPIO MC5B01 93 VDDIO 129 SCANEN PC3D01D
22 NWR0/NWE PC3B02 58 RXD0/MPIO MC5B01 94 PWM1/MPIO MC5B01 130 TEST PC3D01D
23 ADD19 PC3T02 59 SCK0/MPIO MC5B01 95 PWM2/MPIO MC5B01 131 TMS PC3D21U
24 ADD18 PC3T02 60 TXD1/MPIO MC5B01 96 PWM3/MPIO MC5B01 132 TDO PC3T03
25 ADD7 PC3T02 61 RXD1/MPIO MC5B01 97 CAPT0/MPIO MC5B01 133 TDI PC3D21U
26 ADD6 PC3T02 62 SCK1/MPIO MC5B01 98 CAPT1/MPIO MC5B01 134 TCK PC3D21U
27 GND
(2)
63 VDDIO 99 NRESET MC5D20 135 NWAIT PC3D01U
28 VDDCORE
(1)
64 SPCK/MPIO MC5B01 100 CANRX0 MC5D00 136 ADD21/CS6 PC3T02
29 ADD2 PC3T02 65 MISO/MPIO MC5B01 101 CANTX0 MC5O01 137 NCS3 PC3T02
30 ADD3 PC3T02 66 MOSI/MPIO MC5B01 102 TXD2/MPIO MC5B01 138 NCS2 PC3T02
31 ADD4 PC3T02 67 NPCS0/MPIO MC5B01 103 RXD2/MPIO MC5B01 139 NWR1/NUB PC3B02
32 ADD5 PC3T02 68 NPCS1/MPIO MC5B01 104 SCK2/MPIO MC5B01 140 ADD0/NLB PC3T02
33 ADD8 PC3T02 69 NPCS2/MPIO MC5B01 105 GND 141 NCS1 PC3T02
34 ADD20/CS7 PC3T02 70 NPCS3/MPIO MC5B01 106 VDDANA 142 NOE/NRD PC3B02
35 ADD9 PC3T02 71 PIOA0 MC5B04 107 VREFP ANAIN 143 NCS0 PC3T02
36 ADD10 PC3T02 72 PIOA1 MC5B04 108 ANA0IN0 AIMUX1 144 ADD1 PC3T02
5
6048C–ATARM–29-Jun-06
AT91SAM7A1
4. Pin Description
Table 4-1. Pin Description
Module Name Function Type
(1)
Level
(1)
Comments
EBI
(2)
ADD[19:1] External address bus O (Z)
The EBI is tri-stated when NRESET is
at a logical low level. Internal pull-
downs on data bus bits. ADD20 and
ADD21 are address lines at reset.
ADD0/NLB
External address line/Lower
byte enable
OL (Z)
ADD20/CS7
External address line/Chip
select
OH (Z)
ADD21/CS6
External address line/Chip
select
OH (Z)
D[15:0]
(3)
External data bus I/O (Z)
NOE/NRD Output enable O L (Z)
NWR0/NWE Write enable O L (Z)
NCS[3:0] Chip select lines O L (Z)
NWR1/NUB Upper byte enable O L (Z)
NWAIT Wait Input I L
Internal pull-up (must be connected to
VCC or leave unconnected for normal
operation)
GIC
IRQ0 External interrupt line I
FIQ Fast interrupt line I
Power-on
Reset
NRESET Hardware reset input I L Schmitt input with internal filter
Master
Clock
MCKI Master clock input I
Connected to external crystal (4 to 16
MHz)
MCKO Master clock output O
PLLRC PLL RC network input I
Real-time
Clock
RTCKI 32.768 kHz clock input I
Connected to external 32.768 kHz
crystal
RTCKO 32.768 kHz clock output O
UPIO UPIO[17:0] Unified I/O I/O (I) (Z) General-purpose I/O
USART0
SCK0/MPIO USART0 clock line I/O (I) (Z) Multiplexed with general-purpose I/O
RXD0/MPIO USART0 receive line I/O (I) (Z) Multiplexed with general-purpose I/O
TXD0/MPIO USART0 transmit line I/O (I) (Z) Multiplexed with general-purpose I/O
USART1
SCK1/MPIO USART1 clock line I/O (I) (Z) Multiplexed with general-purpose I/O
RXD1/MPIO USART1 receive line I/O (I) (Z) Multiplexed with general-purpose I/O
TXD1/MPIO USART1 transmit line I/O (I) (Z) Multiplexed with general-purpose I/O
USART2
SCK2/MPIO USART2 clock line I/O (I) (Z) Multiplexed with general-purpose I/O
RXD2/MPIO USART2 receive line I/O (I) (Z) Multiplexed with general-purpose I/O
TXD2/MPIO USART2 transmit line I/O (I) (Z) Multiplexed with general-purpose I/O
Capture CAPT[1:0]/MPIO Capture input I/O (I) (Z) Multiplexed with general-purpose I/O
PWM PWM[3:0]/MPIO Pulse Width Modulation output I/O (I) (Z) Multiplexed with general-purpose I/O
6
6048C–ATARM–29-Jun-06
AT91SAM7A1
Notes: 1. Values in brackets are values at reset H (high level), L (low level), Z (tri-state), I (input), O (output).
2. The EBI bus (address bus A[21:0], data bus D[15:0] and control lines NOE/NRD, NWR0/NWE, NWR1/NUB and NCS[3:0]) is
tri-stated when NRESET is at a logical 0. This allows external equipment to access the external memory devices (e.g., for
Flash programming). It is up to the application to add an external pull-up on the chip select lines in order to avoid EBI con-
flicts at reset.
3. The EBI data bus D[15:0] has an internal pull-down.
Timer T0
T0TIOA[2:0]/MPIO Capture/waveform I/O I/O (I) (Z) Multiplexed with a general-purpose I/O
T0TIOB[2:0]/MPIO Trigger/waveform I/O I/O (I) (Z) Multiplexed with a general-purpose I/O
T0TCLK[2:0]/MPIO External clock/trigger/input I/O (I) (Z) Multiplexed with a general-purpose I/O
ADC
ANAIN[7:0] Analog input I
VREFP Positive voltage reference I
SPI
SPCK/MPIO SPI clock line I/O (I) (Z) Multiplexed with a general-purpose I/O
MISO/MPIO SPI master in slave out I/O (I) (Z) Multiplexed with a general-purpose I/O
MOSI/MPIO SPI master out slave in I/O (I) (Z) Multiplexed with a general-purpose I/O
NPCS[3:1]/MPIO SPI chip select I/O (I) (Z) Multiplexed with a general-purpose I/O
NPCS0/MPIO SPI chip select I/O (I) (Z) Multiplexed with a general-purpose I/O
CAN0
CANRX0 CAN0 receive line I L
CANTX0 CAN0 transmit line O L (H)
JTAG
SCANEN Scan enable (Factory test) I H
Internal pull-down (must be connected
to GND or leave unconnected for
normal operation)
TDI Test Data In I Schmitt trigger, internal pull-up
TDO Test Data Out O
TMS Test Mode Select I Schmitt trigger, internal pull-up
TCK Test Clock I Schmitt trigger, internal pull-up
TEST Factory test I H
Internal pull-down (must be connected
to GND or leave unconnected for
normal operation)
Power
Supplies
VDDCORE Core Power Supply – 3.3V
VDDANA Analog Power Supply – 3.3V
VDDIO I/O Lines Power Supply – 3.3V to 5V
GND Ground –
Table 4-1. Pin Description
Module Name Function Type
(1)
Level
(1)
Comments
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AT91SAM7A1-AU

Mfr. #:
Buy AT91SAM7A1-AU
Manufacturer:
Microchip Technology / Atmel
Description:
ARM Microcontrollers - MCU LQFP GREEN IND TEMP
Lifecycle:
New from this manufacturer.
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